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llvm-mirror/test/MC/Disassembler/ARM
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Johnny Chen 6e8aeaa2f4 Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx 
Modified the patch to .td file supplied by Jyun-Yan You.  Add a test case and
modified ARMDisassemblerCore.cpp a little bit.

llvm-svn: 131859
2011-05-22 17:51:04 +00:00
..
arm-tests.txt Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx 2011-05-22 17:51:04 +00:00
dg.exp
invalid-Bcc-thumb.txt A8.6.16 B 2011-04-12 00:14:49 +00:00
invalid-BFI-arm.txt Add sanity checking for bad register specifier(s) for the DPFrm instructions. 2011-04-08 00:29:09 +00:00
invalid-CPS2p-arm.txt
invalid-CPS3p-arm.txt
invalid-DMB-thumb.txt Sanity check the option operand for DMB/DSB. 2011-04-08 19:18:07 +00:00
invalid-DSB-arm.txt Sanity check the option operand for DMB/DSB. 2011-04-08 19:18:07 +00:00
invalid-LDC-form-arm.txt
invalid-LDR_POST-arm.txt Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as 2011-04-11 18:34:12 +00:00
invalid-LDR_PRE-arm.txt Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as 2011-04-11 18:34:12 +00:00
invalid-LDRB_POST-arm.txt Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as 2011-04-11 18:34:12 +00:00
invalid-LDRD_PRE-thumb.txt Add sanity check for Ld/St Dual forms of Thumb2 instructions. 2011-04-12 23:31:00 +00:00
invalid-LDRrs-arm.txt
invalid-LDRT-arm.txt
invalid-LSL-regform.txt Add some more comments about checkings of invalid register numbers. 2011-04-07 18:33:19 +00:00
invalid-MCR-arm.txt A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" 2011-04-06 20:49:02 +00:00
invalid-MOVr-arm.txt
invalid-MOVs-arm.txt
invalid-MOVs-LSL-arm.txt
invalid-MOVTi16-arm.txt MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it. 2011-04-08 17:29:58 +00:00
invalid-MSRi-arm.txt Sanity check MSRi for invalid mask values and reject it as invalid. 2011-04-07 01:37:34 +00:00
invalid-RFEorLDMIA-arm.txt
invalid-RSC-arm.txt
invalid-SBFX-arm.txt Add sanity checking for bad register specifier(s) for the DPFrm instructions. 2011-04-08 00:29:09 +00:00
invalid-SMLAD-arm.txt Should also check SMLAD for invalid register values. 2011-04-07 00:50:25 +00:00
invalid-SRS-arm.txt
invalid-SSAT-arm.txt Add sanity checking for invalid register encodings for saturating instructions. 2011-04-07 19:02:08 +00:00
invalid-STMIA_UPD-thumb.txt Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple. 2011-04-12 17:09:04 +00:00
invalid-STRBrs-arm.txt Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as 2011-04-11 18:34:12 +00:00
invalid-SXTB-arm.txt Add sanity checking for invalid register encodings for signed/unsigned extend instructions. 2011-04-07 19:28:58 +00:00
invalid-t2Bcc-thumb.txt Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc). 2011-04-13 21:35:49 +00:00
invalid-t2LDRBT-thumb.txt The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt. 2011-04-13 21:04:32 +00:00
invalid-t2LDREXD-thumb.txt Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. 2011-04-14 19:13:28 +00:00
invalid-t2LDRSHi8-thumb.txt Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such. 2011-04-13 19:46:05 +00:00
invalid-t2LDRSHi12-thumb.txt Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such. 2011-04-13 19:46:05 +00:00
invalid-t2STR_POST-thumb.txt Add bad register checks for Thumb2 Ld/St instructions. 2011-04-12 21:17:51 +00:00
invalid-t2STRD_PRE-thumb.txt Add sanity check for Ld/St Dual forms of Thumb2 instructions. 2011-04-12 23:31:00 +00:00
invalid-t2STREXB-thumb.txt Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. 2011-04-14 19:13:28 +00:00
invalid-t2STREXD-thumb.txt Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. 2011-04-14 19:13:28 +00:00
invalid-UMAAL-arm.txt
invalid-UQADD8-arm.txt Add sanity checking for bad register specifier(s) for the DPFrm instructions. 2011-04-08 00:29:09 +00:00
invalid-VLD1DUPq8_UPD-arm.txt The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions 2011-04-15 00:10:45 +00:00
invalid-VLD3DUPd32_UPD-thumb.txt A8.6.315 VLD3 (single 3-element structure to all lanes) 2011-04-15 22:49:08 +00:00
invalid-VLDMSDB_UPD-arm.txt
invalid-VQADD-arm.txt A7.3 register encoding 2011-04-05 22:57:07 +00:00
invalid-VST2b32_UPD-arm.txt A8.6.393 2011-04-06 22:14:48 +00:00
neon-tests.txt The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions 2011-04-15 00:10:45 +00:00
thumb-printf.txt Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should 2011-04-22 19:12:43 +00:00
thumb-tests.txt Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand. 2011-05-18 20:32:41 +00:00