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db0ecdf907
Some conditional branch instructions generated by this pass are checking the wrong condition code. The instructions TBZ and TBNZ are transformed into B.GE and B.LT instead of B.PL and B.MI respectively. They should only be checking the Negative bit. Differential Revision: https://reviews.llvm.org/D34743 llvm-svn: 306550
170 lines
3.4 KiB
LLVM
170 lines
3.4 KiB
LLVM
; RUN: llc < %s -O3 -mtriple=aarch64-eabi -verify-machineinstrs | FileCheck %s
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-linaro-linux-gnueabi"
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; CMN is an alias of ADDS.
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; CHECK-LABEL: test_add_cbz:
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; CHECK: cmn w0, w1
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; CHECK: b.eq
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; CHECK: ret
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define void @test_add_cbz(i32 %a, i32 %b, i32* %ptr) {
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%c = add nsw i32 %a, %b
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%d = icmp ne i32 %c, 0
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br i1 %d, label %L1, label %L2
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L1:
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store i32 0, i32* %ptr, align 4
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ret void
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L2:
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store i32 1, i32* %ptr, align 4
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ret void
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}
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; CHECK-LABEL: test_add_cbz_multiple_use:
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; CHECK: adds
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; CHECK: b.eq
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; CHECK: ret
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define void @test_add_cbz_multiple_use(i32 %a, i32 %b, i32* %ptr) {
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%c = add nsw i32 %a, %b
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%d = icmp ne i32 %c, 0
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br i1 %d, label %L1, label %L2
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L1:
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store i32 0, i32* %ptr, align 4
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ret void
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L2:
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store i32 %c, i32* %ptr, align 4
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ret void
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}
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; CHECK-LABEL: test_add_cbz_64:
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; CHECK: cmn x0, x1
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; CHECK: b.eq
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define void @test_add_cbz_64(i64 %a, i64 %b, i64* %ptr) {
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%c = add nsw i64 %a, %b
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%d = icmp ne i64 %c, 0
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br i1 %d, label %L1, label %L2
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L1:
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store i64 0, i64* %ptr, align 4
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ret void
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L2:
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store i64 1, i64* %ptr, align 4
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ret void
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}
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; CHECK-LABEL: test_and_cbz:
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; CHECK: tst w0, #0x6
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; CHECK: b.eq
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define void @test_and_cbz(i32 %a, i32* %ptr) {
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%c = and i32 %a, 6
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%d = icmp ne i32 %c, 0
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br i1 %d, label %L1, label %L2
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L1:
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store i32 0, i32* %ptr, align 4
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ret void
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L2:
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store i32 1, i32* %ptr, align 4
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ret void
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}
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; CHECK-LABEL: test_bic_cbnz:
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; CHECK: bics wzr, w1, w0
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; CHECK: b.ne
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define void @test_bic_cbnz(i32 %a, i32 %b, i32* %ptr) {
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%c = and i32 %a, %b
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%d = icmp eq i32 %c, %b
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br i1 %d, label %L1, label %L2
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L1:
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store i32 0, i32* %ptr, align 4
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ret void
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L2:
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store i32 1, i32* %ptr, align 4
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ret void
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}
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; CHECK-LABEL: test_add_tbz:
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; CHECK: adds
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; CHECK: b.pl
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; CHECK: ret
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define void @test_add_tbz(i32 %a, i32 %b, i32* %ptr) {
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entry:
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%add = add nsw i32 %a, %b
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%cmp36 = icmp sge i32 %add, 0
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br i1 %cmp36, label %L2, label %L1
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L1:
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store i32 %add, i32* %ptr, align 8
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br label %L2
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L2:
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ret void
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}
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; CHECK-LABEL: test_subs_tbz:
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; CHECK: subs
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; CHECK: b.pl
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; CHECK: ret
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define void @test_subs_tbz(i32 %a, i32 %b, i32* %ptr) {
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entry:
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%sub = sub nsw i32 %a, %b
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%cmp36 = icmp sge i32 %sub, 0
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br i1 %cmp36, label %L2, label %L1
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L1:
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store i32 %sub, i32* %ptr, align 8
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br label %L2
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L2:
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ret void
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}
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; CHECK-LABEL: test_add_tbnz
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; CHECK: adds
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; CHECK: b.mi
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; CHECK: ret
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define void @test_add_tbnz(i32 %a, i32 %b, i32* %ptr) {
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entry:
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%add = add nsw i32 %a, %b
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%cmp36 = icmp slt i32 %add, 0
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br i1 %cmp36, label %L2, label %L1
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L1:
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store i32 %add, i32* %ptr, align 8
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br label %L2
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L2:
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ret void
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}
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; CHECK-LABEL: test_subs_tbnz
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; CHECK: subs
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; CHECK: b.mi
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; CHECK: ret
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define void @test_subs_tbnz(i32 %a, i32 %b, i32* %ptr) {
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entry:
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%sub = sub nsw i32 %a, %b
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%cmp36 = icmp slt i32 %sub, 0
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br i1 %cmp36, label %L2, label %L1
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L1:
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store i32 %sub, i32* %ptr, align 8
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br label %L2
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L2:
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ret void
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}
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declare void @foo()
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declare void @bar(i32)
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; Don't transform since the call will clobber the NZCV bits.
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; CHECK-LABEL: test_call_clobber:
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; CHECK: and w[[DST:[0-9]+]], w1, #0x6
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; CHECK: bl bar
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; CHECK: cbnz w[[DST]]
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define void @test_call_clobber(i32 %unused, i32 %a) {
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entry:
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%c = and i32 %a, 6
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call void @bar(i32 %c)
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%tobool = icmp eq i32 %c, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then:
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tail call void @foo()
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unreachable
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if.end:
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ret void
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}
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