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An encoding does not allow to use SDWA in an instruction with scalar operands, either literals or SGPRs. That is however possible to copy these operands into a VGPR first. Several copies of the value are produced if multiple SDWA conversions were done. To cleanup MachineLICM (to hoist copies out of loops), MachineCSE (to remove duplicate copies) and SIFoldOperands (to replace SGPR to VGPR copy with immediate copy right to the VGPR) runs are added after the SDWA pass. Differential Revision: https://reviews.llvm.org/D33583 llvm-svn: 304219
50 lines
2.6 KiB
LLVM
50 lines
2.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=fiji -amdgpu-sdwa-peephole=0 < %s | FileCheck --check-prefix=GCN --check-prefix=VI %s
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; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GCN --check-prefix=VI-SDWA %s
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; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck --check-prefix=GCN --check-prefix=CI %s
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; GCN-LABEL: {{^}}bfe_combine8:
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; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 8, 8
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; VI: v_lshlrev_b32_e32 v[[ADDRBASE:[0-9]+]], 2, v[[BFE]]
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; VI-SDWA: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 2
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; VI-SDWA: v_lshlrev_b32_sdwa v[[ADDRBASE:[0-9]+]], v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
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; CI: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 6, v{{[0-9]+}}
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; CI: v_and_b32_e32 v[[ADDRLO:[0-9]+]], 0x3fc, v[[SHR]]
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; VI: v_add_i32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]]
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; VI-SDWA: v_add_i32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]]
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; GCN: load_dword v{{[0-9]+}}, v{{\[}}[[ADDRLO]]:
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define amdgpu_kernel void @bfe_combine8(i32 addrspace(1)* nocapture %arg, i32 %x) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x() #2
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%idx = add i32 %x, %id
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%srl = lshr i32 %idx, 8
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%and = and i32 %srl, 255
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%ptr = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %and
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%val = load i32, i32 addrspace(1)* %ptr, align 4
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store i32 %val, i32 addrspace(1)* %arg, align 4
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ret void
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}
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; GCN-LABEL: {{^}}bfe_combine16:
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; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 16, 16
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; VI: v_lshlrev_b32_e32 v[[ADDRBASE:[0-9]+]], {{[^,]+}}, v[[BFE]]
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; VI-SDWA: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 15
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; VI-SDWA: v_lshlrev_b32_sdwa v[[ADDRBASE1:[0-9]+]], v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
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; VI-SDWA: v_lshlrev_b64 v{{\[}}[[ADDRBASE:[0-9]+]]:{{[^\]+}}], 2, v{{\[}}[[ADDRBASE1]]:{{[^\]+}}]
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; VI-SDWA: v_add_i32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]]
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; CI: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 1, v{{[0-9]+}}
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; CI: v_and_b32_e32 v[[AND:[0-9]+]], 0x7fff8000, v[[SHR]]
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; CI: v_lshl_b64 v{{\[}}[[ADDRLO:[0-9]+]]:{{[^\]+}}], v{{\[}}[[AND]]:{{[^\]+}}], 2
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; VI: v_add_i32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]]
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; GCN: load_dword v{{[0-9]+}}, v{{\[}}[[ADDRLO]]:
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define amdgpu_kernel void @bfe_combine16(i32 addrspace(1)* nocapture %arg, i32 %x) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x() #2
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%idx = add i32 %x, %id
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%srl = lshr i32 %idx, 1
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%and = and i32 %srl, 2147450880
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%ptr = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %and
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%val = load i32, i32 addrspace(1)* %ptr, align 4
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store i32 %val, i32 addrspace(1)* %arg, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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