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3a9e77fc0f
Summary: LC can currently select scalar load for uniform memory access basing on readonly memory address space only. This restriction originated from the fact that in HW prior to VI vector and scalar caches are not coherent. With MemoryDependenceAnalysis we can check that the memory location corresponding to the memory operand of the LOAD is not clobbered along the all paths from the function entry. Reviewers: rampitec, tstellarAMD, arsenm Subscribers: wdng, arsenm, nhaehnle Differential Revision: https://reviews.llvm.org/D26917 llvm-svn: 289076
127 lines
4.9 KiB
LLVM
127 lines
4.9 KiB
LLVM
; RUN: llc -O2 -mtriple amdgcn--amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads=true -verify-machineinstrs < %s | FileCheck %s
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; uniform loads
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; CHECK-LABEL: @uniform_load
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; CHECK: s_load_dwordx4
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; CHECK-NOT: flat_load_dword
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define amdgpu_kernel void @uniform_load(float addrspace(1)* %arg, float addrspace(1)* %arg1) {
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bb:
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%tmp2 = load float, float addrspace(1)* %arg, align 4, !tbaa !8
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%tmp3 = fadd float %tmp2, 0.000000e+00
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%tmp4 = getelementptr inbounds float, float addrspace(1)* %arg, i64 1
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%tmp5 = load float, float addrspace(1)* %tmp4, align 4, !tbaa !8
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%tmp6 = fadd float %tmp3, %tmp5
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%tmp7 = getelementptr inbounds float, float addrspace(1)* %arg, i64 2
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%tmp8 = load float, float addrspace(1)* %tmp7, align 4, !tbaa !8
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%tmp9 = fadd float %tmp6, %tmp8
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%tmp10 = getelementptr inbounds float, float addrspace(1)* %arg, i64 3
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%tmp11 = load float, float addrspace(1)* %tmp10, align 4, !tbaa !8
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%tmp12 = fadd float %tmp9, %tmp11
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%tmp13 = getelementptr inbounds float, float addrspace(1)* %arg1
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store float %tmp12, float addrspace(1)* %tmp13, align 4, !tbaa !8
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ret void
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}
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; non-uniform loads
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; CHECK-LABEL: @non-uniform_load
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; CHECK: flat_load_dword
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; CHECK-NOT: s_load_dwordx4
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define amdgpu_kernel void @non-uniform_load(float addrspace(1)* %arg, float addrspace(1)* %arg1) #0 {
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bb:
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%tmp = call i32 @llvm.amdgcn.workitem.id.x() #1
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%tmp2 = getelementptr inbounds float, float addrspace(1)* %arg, i32 %tmp
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%tmp3 = load float, float addrspace(1)* %tmp2, align 4, !tbaa !8
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%tmp4 = fadd float %tmp3, 0.000000e+00
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%tmp5 = add i32 %tmp, 1
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%tmp6 = getelementptr inbounds float, float addrspace(1)* %arg, i32 %tmp5
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%tmp7 = load float, float addrspace(1)* %tmp6, align 4, !tbaa !8
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%tmp8 = fadd float %tmp4, %tmp7
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%tmp9 = add i32 %tmp, 2
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%tmp10 = getelementptr inbounds float, float addrspace(1)* %arg, i32 %tmp9
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%tmp11 = load float, float addrspace(1)* %tmp10, align 4, !tbaa !8
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%tmp12 = fadd float %tmp8, %tmp11
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%tmp13 = add i32 %tmp, 3
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%tmp14 = getelementptr inbounds float, float addrspace(1)* %arg, i32 %tmp13
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%tmp15 = load float, float addrspace(1)* %tmp14, align 4, !tbaa !8
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%tmp16 = fadd float %tmp12, %tmp15
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%tmp17 = getelementptr inbounds float, float addrspace(1)* %arg1, i32 %tmp
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store float %tmp16, float addrspace(1)* %tmp17, align 4, !tbaa !8
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ret void
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}
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; uniform load dominated by no-alias store - scalarize
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; CHECK-LABEL: @no_memdep_alias_arg
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; CHECK: flat_store_dword
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; CHECK: s_load_dword [[SVAL:s[0-9]+]]
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; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[SVAL]]
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; CHECK: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[VVAL]]
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define amdgpu_kernel void @no_memdep_alias_arg(i32 addrspace(1)* noalias %in, i32 addrspace(1)* %out0, i32 addrspace(1)* %out1) {
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store i32 0, i32 addrspace(1)* %out0
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%val = load i32, i32 addrspace(1)* %in
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store i32 %val, i32 addrspace(1)* %out1
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ret void
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}
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; uniform load dominated by alias store - vector
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; CHECK-LABEL: {{^}}memdep:
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; CHECK: flat_store_dword
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; CHECK: flat_load_dword [[VVAL:v[0-9]+]]
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; CHECK: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[VVAL]]
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define amdgpu_kernel void @memdep(i32 addrspace(1)* %in, i32 addrspace(1)* %out0, i32 addrspace(1)* %out1) {
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store i32 0, i32 addrspace(1)* %out0
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%val = load i32, i32 addrspace(1)* %in
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store i32 %val, i32 addrspace(1)* %out1
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ret void
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}
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; uniform load from global array
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; CHECK-LABEL: @global_array
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; CHECK: s_load_dwordx2 [[A_ADDR:s\[[0-9]+:[0-9]+\]]]
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; CHECK: s_load_dwordx2 [[A_ADDR1:s\[[0-9]+:[0-9]+\]]], [[A_ADDR]], 0x0
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; CHECK: s_load_dword [[SVAL:s[0-9]+]], [[A_ADDR1]], 0x0
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; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[SVAL]]
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; CHECK: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[VVAL]]
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@A = common local_unnamed_addr addrspace(1) global i32 addrspace(1)* null, align 4
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define amdgpu_kernel void @global_array(i32 addrspace(1)* nocapture %out) {
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entry:
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%0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* @A, align 4
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%1 = load i32, i32 addrspace(1)* %0, align 4
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store i32 %1, i32 addrspace(1)* %out, align 4
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ret void
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}
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; uniform load from global array dominated by alias store
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; CHECK-LABEL: @global_array_alias_store
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; CHECK: flat_store_dword
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; CHECK: v_mov_b32_e32 v[[ADDR_LO:[0-9]+]], s{{[0-9]+}}
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; CHECK: v_mov_b32_e32 v[[ADDR_HI:[0-9]+]], s{{[0-9]+}}
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; CHECK: flat_load_dwordx2 [[A_ADDR:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[ADDR_LO]]:[[ADDR_HI]]{{\]}}
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; CHECK: flat_load_dword [[VVAL:v[0-9]+]], [[A_ADDR]]
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; CHECK: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[VVAL]]
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define amdgpu_kernel void @global_array_alias_store(i32 addrspace(1)* nocapture %out, i32 %n) {
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entry:
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%gep = getelementptr i32, i32 addrspace(1) * %out, i32 %n
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store i32 12, i32 addrspace(1) * %gep
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%0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* @A, align 4
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%1 = load i32, i32 addrspace(1)* %0, align 4
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store i32 %1, i32 addrspace(1)* %out, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #1 = { nounwind readnone }
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!8 = !{!9, !9, i64 0}
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!9 = !{!"float", !10, i64 0}
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!10 = !{!"omnipotent char", !11, i64 0}
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!11 = !{!"Simple C/C++ TBAA"}
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