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5dfc642fbd
Try to avoid mutually exclusive features. Don't use a real default GPU, and use a fake "generic". The goal is to make it easier to see which set of features are incompatible between feature strings. Most of the test changes are due to random scheduling changes from not having a default fullspeed model. llvm-svn: 310258
111 lines
4.3 KiB
LLVM
111 lines
4.3 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}round_f32:
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; GCN-DAG: s_load_dword [[SX:s[0-9]+]]
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; GCN-DAG: s_brev_b32 [[K:s[0-9]+]], -2{{$}}
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; GCN-DAG: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[SX]]
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; GCN-DAG: v_sub_f32_e32 [[SUB:v[0-9]+]], [[SX]], [[TRUNC]]
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; GCN-DAG: v_mov_b32_e32 [[VX:v[0-9]+]], [[SX]]
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; GCN: v_bfi_b32 [[COPYSIGN:v[0-9]+]], [[K]], 1.0, [[VX]]
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; GCN: v_cmp_ge_f32_e64 vcc, |[[SUB]]|, 0.5
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; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, [[VX]]
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; GCN: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TRUNC]], [[SEL]]
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; GCN: buffer_store_dword [[RESULT]]
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; R600: TRUNC {{.*}}, [[ARG:KC[0-9]\[[0-9]+\]\.[XYZW]]]
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; R600-DAG: ADD {{.*}},
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; R600-DAG: BFI_INT
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; R600-DAG: SETGE
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; R600-DAG: CNDE
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; R600-DAG: ADD
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define amdgpu_kernel void @round_f32(float addrspace(1)* %out, float %x) #0 {
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%result = call float @llvm.round.f32(float %x) #1
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store float %result, float addrspace(1)* %out
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ret void
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}
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; The vector tests are really difficult to verify, since it can be hard to
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; predict how the scheduler will order the instructions. We already have
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; a test for the scalar case, so the vector tests just check that the
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; compiler doesn't crash.
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; FUNC-LABEL: {{^}}round_v2f32:
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; GCN: s_endpgm
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; R600: CF_END
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define amdgpu_kernel void @round_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) #0 {
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%result = call <2 x float> @llvm.round.v2f32(<2 x float> %in) #1
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store <2 x float> %result, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}round_v4f32:
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; GCN: s_endpgm
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; R600: CF_END
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define amdgpu_kernel void @round_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) #0 {
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%result = call <4 x float> @llvm.round.v4f32(<4 x float> %in) #1
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}round_v8f32:
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; GCN: s_endpgm
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; R600: CF_END
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define amdgpu_kernel void @round_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %in) #0 {
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%result = call <8 x float> @llvm.round.v8f32(<8 x float> %in) #1
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store <8 x float> %result, <8 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}round_f16:
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; GFX89-DAG: s_load_dword [[SX:s[0-9]+]]
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; GFX89-DAG: s_movk_i32 [[K:s[0-9]+]], 0x7fff{{$}}
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; GFX89-DAG: v_mov_b32_e32 [[VX:v[0-9]+]], [[SX]]
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; GFX89-DAG: v_mov_b32_e32 [[BFI_K:v[0-9]+]], 0x3c00
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; GFX89: v_bfi_b32 [[COPYSIGN:v[0-9]+]], [[K]], [[BFI_K]], [[VX]]
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; GFX89: v_trunc_f16_e32 [[TRUNC:v[0-9]+]], [[SX]]
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; GFX89: v_sub_f16_e32 [[SUB:v[0-9]+]], [[SX]], [[TRUNC]]
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; GFX89: v_cmp_ge_f16_e64 vcc, |[[SUB]]|, 0.5
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; GFX89: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, [[COPYSIGN]]
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; GFX89: v_add_f16_e32 [[RESULT:v[0-9]+]], [[TRUNC]], [[SEL]]
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; GFX89: buffer_store_short [[RESULT]]
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define amdgpu_kernel void @round_f16(half addrspace(1)* %out, i32 %x.arg) #0 {
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%x.arg.trunc = trunc i32 %x.arg to i16
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%x = bitcast i16 %x.arg.trunc to half
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%result = call half @llvm.round.f16(half %x) #1
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store half %result, half addrspace(1)* %out
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ret void
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}
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; Should be scalarized
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; FUNC-LABEL: {{^}}round_v2f16:
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; GFX89-DAG: s_movk_i32 [[K:s[0-9]+]], 0x7fff{{$}}
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; GFX89-DAG: v_mov_b32_e32 [[BFI_K:v[0-9]+]], 0x3c00
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; GFX89: v_bfi_b32 [[COPYSIGN0:v[0-9]+]], [[K]], [[BFI_K]],
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; GFX89: v_bfi_b32 [[COPYSIGN1:v[0-9]+]], [[K]], [[BFI_K]],
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; GFX9: v_and_b32_e32
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; GFX9: v_lshl_or_b32
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define amdgpu_kernel void @round_v2f16(<2 x half> addrspace(1)* %out, i32 %in.arg) #0 {
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%in = bitcast i32 %in.arg to <2 x half>
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%result = call <2 x half> @llvm.round.v2f16(<2 x half> %in)
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store <2 x half> %result, <2 x half> addrspace(1)* %out
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ret void
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}
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declare float @llvm.round.f32(float) #1
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declare <2 x float> @llvm.round.v2f32(<2 x float>) #1
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declare <4 x float> @llvm.round.v4f32(<4 x float>) #1
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declare <8 x float> @llvm.round.v8f32(<8 x float>) #1
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declare half @llvm.round.f16(half) #1
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declare <2 x half> @llvm.round.v2f16(<2 x half>) #1
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declare <4 x half> @llvm.round.v4f16(<4 x half>) #1
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declare <8 x half> @llvm.round.v8f16(<8 x half>) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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