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fbfa163a41
MachineScheduler when clustering loads or stores checks if base pointers point to the same memory. This check is done through comparison of base registers of two memory instructions. This works fine when instructions have separate offset operand. If they require a full calculated pointer such instructions can never be clustered according to such logic. Changed shouldClusterMemOps to accept base registers as well and let it decide what to do about it. Differential Revision: https://reviews.llvm.org/D37698 llvm-svn: 313208
328 lines
14 KiB
LLVM
328 lines
14 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -enable-amdgpu-aa=0 -verify-machineinstrs -enable-misched -enable-aa-sched-mi < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -enable-amdgpu-aa=0 -verify-machineinstrs -enable-misched -enable-aa-sched-mi < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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declare void @llvm.amdgcn.tbuffer.store.i32(i32, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
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declare void @llvm.amdgcn.tbuffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
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declare void @llvm.amdgcn.s.barrier() #1
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declare i32 @llvm.amdgcn.workitem.id.x() #2
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@stored_lds_ptr = addrspace(3) global i32 addrspace(3)* undef, align 4
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@stored_constant_ptr = addrspace(3) global i32 addrspace(2)* undef, align 8
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@stored_global_ptr = addrspace(3) global i32 addrspace(1)* undef, align 8
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; GCN-LABEL: {{^}}reorder_local_load_global_store_local_load:
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; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:1 offset1:3
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; CI: buffer_store_dword
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; GFX9: global_store_dword
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; GFX9: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:1 offset1:3
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; GFX9: global_store_dword
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define amdgpu_kernel void @reorder_local_load_global_store_local_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
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%ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
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%ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1
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%ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 3
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%tmp1 = load i32, i32 addrspace(3)* %ptr1, align 4
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store i32 99, i32 addrspace(1)* %gptr, align 4
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%tmp2 = load i32, i32 addrspace(3)* %ptr2, align 4
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%add = add nsw i32 %tmp1, %tmp2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}no_reorder_local_load_volatile_global_store_local_load:
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; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:4
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; CI: buffer_store_dword
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; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:12
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; GFX9: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:4
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; GFX9: global_store_dword
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; GFX9: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:12
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define amdgpu_kernel void @no_reorder_local_load_volatile_global_store_local_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
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%ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
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%ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1
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%ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 3
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%tmp1 = load i32, i32 addrspace(3)* %ptr1, align 4
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store volatile i32 99, i32 addrspace(1)* %gptr, align 4
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%tmp2 = load i32, i32 addrspace(3)* %ptr2, align 4
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%add = add nsw i32 %tmp1, %tmp2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}no_reorder_barrier_local_load_global_store_local_load:
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; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:4
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; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:12
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; CI: buffer_store_dword
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; GFX9: global_store_dword
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; GFX9: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:4
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; GFX9: s_barrier
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; GFX9: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:12
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; GFX9: global_store_dword
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define amdgpu_kernel void @no_reorder_barrier_local_load_global_store_local_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
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%ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
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%ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1
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%ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 3
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%tmp1 = load i32, i32 addrspace(3)* %ptr1, align 4
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store i32 99, i32 addrspace(1)* %gptr, align 4
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call void @llvm.amdgcn.s.barrier() #1
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%tmp2 = load i32, i32 addrspace(3)* %ptr2, align 4
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%add = add nsw i32 %tmp1, %tmp2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}reorder_constant_load_global_store_constant_load:
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; GCN-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
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; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
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; CI: buffer_store_dword
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; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x1
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; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x3
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; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x4
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; GFX9: global_store_dword
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; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xc
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; CI: buffer_store_dword
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; GFX9: global_store_dword
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define amdgpu_kernel void @reorder_constant_load_global_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
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%ptr0 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(3)* @stored_constant_ptr, align 8
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%ptr1 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 1
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%ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 3
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%tmp1 = load i32, i32 addrspace(2)* %ptr1, align 4
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store i32 99, i32 addrspace(1)* %gptr, align 4
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%tmp2 = load i32, i32 addrspace(2)* %ptr2, align 4
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%add = add nsw i32 %tmp1, %tmp2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}reorder_constant_load_local_store_constant_load:
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; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
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; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
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; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x1
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; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x3
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; GFX9-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x4
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; GFX9-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xc
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; GCN: ds_write_b32
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; CI: buffer_store_dword
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; GFX9: global_store_dword
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define amdgpu_kernel void @reorder_constant_load_local_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(3)* %lptr) #0 {
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%ptr0 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(3)* @stored_constant_ptr, align 8
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%ptr1 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 1
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%ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 3
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%tmp1 = load i32, i32 addrspace(2)* %ptr1, align 4
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store i32 99, i32 addrspace(3)* %lptr, align 4
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%tmp2 = load i32, i32 addrspace(2)* %ptr2, align 4
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%add = add nsw i32 %tmp1, %tmp2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}reorder_smrd_load_local_store_smrd_load:
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; GCN: s_load_dword
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; GCN: s_load_dword
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; GCN: s_load_dword
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; GCN: ds_write_b32
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; CI: buffer_store_dword
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; GFX9: global_store_dword
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define amdgpu_kernel void @reorder_smrd_load_local_store_smrd_load(i32 addrspace(1)* %out, i32 addrspace(3)* noalias %lptr, i32 addrspace(2)* %ptr0) #0 {
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%ptr1 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 1
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%ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 2
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%tmp1 = load i32, i32 addrspace(2)* %ptr1, align 4
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store i32 99, i32 addrspace(3)* %lptr, align 4
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%tmp2 = load i32, i32 addrspace(2)* %ptr2, align 4
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%add = add nsw i32 %tmp1, %tmp2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}reorder_global_load_local_store_global_load:
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; CI: ds_write_b32
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; CI: buffer_load_dword
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; CI: buffer_load_dword
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; CI: buffer_store_dword
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; GFX9: global_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:4
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; GFX9: global_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:12
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; GFX9: ds_write_b32
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define amdgpu_kernel void @reorder_global_load_local_store_global_load(i32 addrspace(1)* %out, i32 addrspace(3)* %lptr, i32 addrspace(1)* %ptr0) #0 {
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%ptr1 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i64 1
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%ptr2 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i64 3
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%tmp1 = load i32, i32 addrspace(1)* %ptr1, align 4
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store i32 99, i32 addrspace(3)* %lptr, align 4
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%tmp2 = load i32, i32 addrspace(1)* %ptr2, align 4
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%add = add nsw i32 %tmp1, %tmp2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}reorder_local_offsets:
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; GCN: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:100 offset1:102
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; GCN-DAG: ds_write2_b32 {{v[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:3 offset1:100
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; GCN-DAG: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:408
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; CI: buffer_store_dword
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; GFX9: global_store_dword
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; GCN: s_endpgm
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define amdgpu_kernel void @reorder_local_offsets(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* noalias nocapture readnone %gptr, i32 addrspace(3)* noalias nocapture %ptr0) #0 {
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%ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 3
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%ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 100
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%ptr3 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 102
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store i32 123, i32 addrspace(3)* %ptr1, align 4
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%tmp1 = load i32, i32 addrspace(3)* %ptr2, align 4
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%tmp2 = load i32, i32 addrspace(3)* %ptr3, align 4
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store i32 123, i32 addrspace(3)* %ptr2, align 4
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%tmp3 = load i32, i32 addrspace(3)* %ptr1, align 4
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store i32 789, i32 addrspace(3)* %ptr3, align 4
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%add.0 = add nsw i32 %tmp2, %tmp1
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%add.1 = add nsw i32 %add.0, %tmp3
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store i32 %add.1, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}reorder_global_offsets:
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; CI-DAG: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400
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; CI-DAG: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:408
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; CI-DAG: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:12
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; CI-DAG: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400
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; CI-DAG: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:408
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; CI: buffer_store_dword
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; CI: s_endpgm
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; GFX9-DAG: global_load_dword {{v[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:400
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; GFX9-DAG: global_load_dword {{v[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:408
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; GFX9-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, off offset:12
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; GFX9-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, off offset:400
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; GFX9-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, off offset:408
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; GFX9: global_store_dword
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; GFX9: s_endpgm
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define amdgpu_kernel void @reorder_global_offsets(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* noalias nocapture readnone %gptr, i32 addrspace(1)* noalias nocapture %ptr0) #0 {
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%ptr1 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 3
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%ptr2 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 100
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%ptr3 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 102
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store i32 123, i32 addrspace(1)* %ptr1, align 4
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%tmp1 = load i32, i32 addrspace(1)* %ptr2, align 4
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%tmp2 = load i32, i32 addrspace(1)* %ptr3, align 4
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store i32 123, i32 addrspace(1)* %ptr2, align 4
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%tmp3 = load i32, i32 addrspace(1)* %ptr1, align 4
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store i32 789, i32 addrspace(1)* %ptr3, align 4
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%add.0 = add nsw i32 %tmp2, %tmp1
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%add.1 = add nsw i32 %add.0, %tmp3
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store i32 %add.1, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}reorder_global_offsets_addr64_soffset0:
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; CI: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
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; CI-NEXT: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:28{{$}}
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; CI-NEXT: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:44{{$}}
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; CI: v_mov_b32
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; CI: v_mov_b32
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; CI: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CI-NEXT: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:20{{$}}
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; CI: v_add_i32
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; CI: v_add_i32
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; CI: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:36{{$}}
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; CI-NEXT: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:52{{$}}
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; GFX9: global_load_dword {{v[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:12
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; GFX9: global_load_dword {{v[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:28
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; GFX9: global_load_dword {{v[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:44
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; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, off{{$}}
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; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, off offset:20
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; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, off offset:36
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; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, off offset:52
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define amdgpu_kernel void @reorder_global_offsets_addr64_soffset0(i32 addrspace(1)* noalias nocapture %ptr.base) #0 {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%id.ext = sext i32 %id to i64
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%ptr0 = getelementptr inbounds i32, i32 addrspace(1)* %ptr.base, i64 %id.ext
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%ptr1 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 3
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%ptr2 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 5
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%ptr3 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 7
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%ptr4 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 9
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%ptr5 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 11
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%ptr6 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 13
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store i32 789, i32 addrspace(1)* %ptr0, align 4
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%tmp1 = load i32, i32 addrspace(1)* %ptr1, align 4
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store i32 123, i32 addrspace(1)* %ptr2, align 4
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%tmp2 = load i32, i32 addrspace(1)* %ptr3, align 4
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%add.0 = add nsw i32 %tmp1, %tmp2
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store i32 %add.0, i32 addrspace(1)* %ptr4, align 4
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%tmp3 = load i32, i32 addrspace(1)* %ptr5, align 4
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%add.1 = add nsw i32 %add.0, %tmp3
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store i32 %add.1, i32 addrspace(1)* %ptr6, align 4
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ret void
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}
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; XGCN-LABEL: {{^}}reorder_local_load_tbuffer_store_local_load:
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; XCI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}}, 0x4
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; XCI: TBUFFER_STORE_FORMAT
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; XCI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}}, 0x8
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; define amdgpu_vs void @reorder_local_load_tbuffer_store_local_load(i32 addrspace(1)* %out, i32 %a1, i32 %vaddr) #0 {
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; %ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4
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; %ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1
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; %ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 2
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; %tmp1 = load i32, i32 addrspace(3)* %ptr1, align 4
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; %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
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; call void @llvm.amdgcn.tbuffer.store.v4i32(<4 x i32> %vdata, <4 x i32> undef,
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; i32 %vaddr, i32 0, i32 0, i32 32, i32 14, i32 4, i1 1, i1 1)
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; %tmp2 = load i32, i32 addrspace(3)* %ptr2, align 4
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; %add = add nsw i32 %tmp1, %tmp2
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; store i32 %add, i32 addrspace(1)* %out, align 4
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; ret void
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; }
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attributes #0 = { nounwind }
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attributes #1 = { nounwind convergent }
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attributes #2 = { nounwind readnone }
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