mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-29 23:12:55 +01:00
109 lines
4.1 KiB
C++
109 lines
4.1 KiB
C++
//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file was developed by Chris Lattner and is distributed under
|
|
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file defines the interfaces that PPC uses to lower LLVM code into a
|
|
// selection DAG.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
|
|
#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
|
|
|
|
#include "llvm/Target/TargetLowering.h"
|
|
#include "llvm/CodeGen/SelectionDAG.h"
|
|
#include "PPC.h"
|
|
|
|
namespace llvm {
|
|
namespace PPCISD {
|
|
enum NodeType {
|
|
// Start the numbering where the builting ops and target ops leave off.
|
|
FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END,
|
|
|
|
/// FSEL - Traditional three-operand fsel node.
|
|
///
|
|
FSEL,
|
|
|
|
/// FCFID - The FCFID instruction, taking an f64 operand and producing
|
|
/// and f64 value containing the FP representation of the integer that
|
|
/// was temporarily in the f64 operand.
|
|
FCFID,
|
|
|
|
/// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
|
|
/// operand, producing an f64 value containing the integer representation
|
|
/// of that FP value.
|
|
FCTIDZ, FCTIWZ,
|
|
|
|
// VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
|
|
// three v4f32 operands and producing a v4f32 result.
|
|
VMADDFP, VNMSUBFP,
|
|
|
|
/// Hi/Lo - These represent the high and low 16-bit parts of a global
|
|
/// address respectively. These nodes have two operands, the first of
|
|
/// which must be a TargetGlobalAddress, and the second of which must be a
|
|
/// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
|
|
/// though these are usually folded into other nodes.
|
|
Hi, Lo,
|
|
|
|
/// GlobalBaseReg - On Darwin, this node represents the result of the mflr
|
|
/// at function entry, used for PIC code.
|
|
GlobalBaseReg,
|
|
|
|
/// These nodes represent the 32-bit PPC shifts that operate on 6-bit
|
|
/// shift amounts. These nodes are generated by the multi-precision shift
|
|
/// code.
|
|
SRL, SRA, SHL,
|
|
|
|
/// CALL - A function call.
|
|
CALL,
|
|
|
|
/// Return with a flag operand, matched by 'blr'
|
|
RET_FLAG,
|
|
};
|
|
}
|
|
|
|
class PPCTargetLowering : public TargetLowering {
|
|
int VarArgsFrameIndex; // FrameIndex for start of varargs area.
|
|
int ReturnAddrIndex; // FrameIndex for return slot.
|
|
public:
|
|
PPCTargetLowering(TargetMachine &TM);
|
|
|
|
/// getTargetNodeName() - This method returns the name of a target specific
|
|
/// DAG node.
|
|
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
|
|
|
/// LowerOperation - Provide custom lowering hooks for some operations.
|
|
///
|
|
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
|
|
|
|
/// LowerArguments - This hook must be implemented to indicate how we should
|
|
/// lower the arguments for the specified function, into the specified DAG.
|
|
virtual std::vector<SDOperand>
|
|
LowerArguments(Function &F, SelectionDAG &DAG);
|
|
|
|
/// LowerCallTo - This hook lowers an abstract call to a function into an
|
|
/// actual call.
|
|
virtual std::pair<SDOperand, SDOperand>
|
|
LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
|
|
unsigned CC,
|
|
bool isTailCall, SDOperand Callee, ArgListTy &Args,
|
|
SelectionDAG &DAG);
|
|
|
|
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
|
|
MachineBasicBlock *MBB);
|
|
|
|
ConstraintType getConstraintType(char ConstraintLetter) const;
|
|
std::vector<unsigned>
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint,
|
|
MVT::ValueType VT) const;
|
|
bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
|
|
};
|
|
}
|
|
|
|
#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
|