Matt Arsenault 4175888640 GlobalISel: Merge FewerElements for G_BUILD_VECTOR/G_CONCAT_VECTORS ...

This switches from using G_EXTRACT in odd cases to widen with undef
and unmerge.

2020-08-22 10:25:53 -04:00

..

AArch64

[SVE] Lower fixed length UDIV to scalable

2020-08-21 09:01:25 -05:00

AMDGPU

GlobalISel: Merge FewerElements for G_BUILD_VECTOR/G_CONCAT_VECTORS

2020-08-22 10:25:53 -04:00

ARC

[ARC] Fix CodeGen/ARC/brcc.ll

2020-08-15 19:33:35 -07:00

ARM

[ARM][MachineOutliner] Add default mode.

2020-08-20 09:25:33 +02:00

AVR

…

BPF

BPF: add a SimplifyCFG IR pass during generic Scalar/IPO optimization

2020-08-06 13:16:00 -07:00

Generic

[Tests] Be consistent w/definition of statepoint-example

2020-08-14 20:45:48 -07:00

Hexagon

Revert "[BPI] Improve static heuristics for integer comparisons"

2020-08-17 20:44:33 +02:00

Inputs

…

Lanai

…

Mips

Revert "[BPI] Improve static heuristics for integer comparisons"

2020-08-17 20:44:33 +02:00

MIR

[AMDGPU] Reorganize GCN subtarget features for unaligned access

2020-08-21 12:26:31 +02:00

MSP430

…

NVPTX

[NVPTX] Fix typo in lit test

2020-08-17 16:02:11 -04:00

PowerPC

[PowerPC] Support constrained scalar sitofp/uitofp

2020-08-22 02:10:29 +08:00

RISCV

[RISCV] Fix inaccurate annotations on PseudoBRIND

2020-08-21 11:38:42 +01:00

SPARC

…

SystemZ

Revert "[BPI] Improve static heuristics for integer comparisons"

2020-08-17 20:44:33 +02:00

Thumb

…

Thumb2

[ARM] Regenerate mve-vabd.ll test. NFC

2020-08-20 12:24:27 +01:00

VE

[VE] Support f128

2020-08-17 17:26:52 +09:00

WebAssembly

[WebAssembly] Fix FastISel address calculation bug

2020-08-08 15:23:11 -07:00

WinCFGuard

…

WinEH

…

X86

[SelectionDAG] Better legalization for FSHL and FSHR

2020-08-21 10:32:49 +01:00

XCore

…