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f8a414589e
Summary: This clang-tidy check is looking for unsigned integer variables whose initializer starts with an implicit cast from llvm::Register and changes the type of the variable to llvm::Register (dropping the llvm:: where possible). Partial reverts in: X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned& MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register PPCFastISel.cpp - No Register::operator-=() PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned& MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor Manual fixups in: ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned& HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register. PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned& Depends on D65919 Reviewers: arsenm, bogner, craig.topper, RKSimon Reviewed By: arsenm Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65962 llvm-svn: 369041
403 lines
13 KiB
C++
403 lines
13 KiB
C++
//===- R600MergeVectorRegisters.cpp ---------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass merges inputs of swizzeable instructions into vector sharing
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/// common data and/or have enough undef subreg using swizzle abilities.
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///
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/// For instance let's consider the following pseudo code :
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/// %5 = REG_SEQ %1, sub0, %2, sub1, %3, sub2, undef, sub3
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/// ...
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/// %7 = REG_SEQ %1, sub0, %3, sub1, undef, sub2, %4, sub3
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/// (swizzable Inst) %7, SwizzleMask : sub0, sub1, sub2, sub3
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///
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/// is turned into :
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/// %5 = REG_SEQ %1, sub0, %2, sub1, %3, sub2, undef, sub3
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/// ...
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/// %7 = INSERT_SUBREG %4, sub3
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/// (swizzable Inst) %7, SwizzleMask : sub0, sub2, sub1, sub3
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///
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/// This allow regalloc to reduce register pressure for vector registers and
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/// to reduce MOV count.
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "R600Defines.h"
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#include "R600InstrInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <utility>
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "vec-merger"
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static bool isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) {
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assert(MRI.isSSA());
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if (Register::isPhysicalRegister(Reg))
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return false;
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const MachineInstr *MI = MRI.getUniqueVRegDef(Reg);
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return MI && MI->isImplicitDef();
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}
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namespace {
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class RegSeqInfo {
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public:
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MachineInstr *Instr;
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DenseMap<unsigned, unsigned> RegToChan;
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std::vector<unsigned> UndefReg;
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RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
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assert(MI->getOpcode() == R600::REG_SEQUENCE);
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for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) {
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MachineOperand &MO = Instr->getOperand(i);
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unsigned Chan = Instr->getOperand(i + 1).getImm();
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if (isImplicitlyDef(MRI, MO.getReg()))
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UndefReg.push_back(Chan);
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else
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RegToChan[MO.getReg()] = Chan;
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}
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}
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RegSeqInfo() = default;
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bool operator==(const RegSeqInfo &RSI) const {
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return RSI.Instr == Instr;
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}
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};
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class R600VectorRegMerger : public MachineFunctionPass {
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private:
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using InstructionSetMap = DenseMap<unsigned, std::vector<MachineInstr *>>;
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MachineRegisterInfo *MRI;
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const R600InstrInfo *TII = nullptr;
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DenseMap<MachineInstr *, RegSeqInfo> PreviousRegSeq;
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InstructionSetMap PreviousRegSeqByReg;
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InstructionSetMap PreviousRegSeqByUndefCount;
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bool canSwizzle(const MachineInstr &MI) const;
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bool areAllUsesSwizzeable(unsigned Reg) const;
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void SwizzleInput(MachineInstr &,
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const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const;
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bool tryMergeVector(const RegSeqInfo *Untouched, RegSeqInfo *ToMerge,
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std::vector<std::pair<unsigned, unsigned>> &Remap) const;
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bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
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std::vector<std::pair<unsigned, unsigned>> &RemapChan);
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bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
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std::vector<std::pair<unsigned, unsigned>> &RemapChan);
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MachineInstr *RebuildVector(RegSeqInfo *MI, const RegSeqInfo *BaseVec,
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const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const;
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void RemoveMI(MachineInstr *);
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void trackRSI(const RegSeqInfo &RSI);
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public:
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static char ID;
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R600VectorRegMerger() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override {
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return "R600 Vector Registers Merge Pass";
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}
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bool runOnMachineFunction(MachineFunction &Fn) override;
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};
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} // end anonymous namespace
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INITIALIZE_PASS_BEGIN(R600VectorRegMerger, DEBUG_TYPE,
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"R600 Vector Reg Merger", false, false)
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INITIALIZE_PASS_END(R600VectorRegMerger, DEBUG_TYPE,
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"R600 Vector Reg Merger", false, false)
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char R600VectorRegMerger::ID = 0;
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char &llvm::R600VectorRegMergerID = R600VectorRegMerger::ID;
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bool R600VectorRegMerger::canSwizzle(const MachineInstr &MI)
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const {
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if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
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return true;
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switch (MI.getOpcode()) {
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case R600::R600_ExportSwz:
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case R600::EG_ExportSwz:
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return true;
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default:
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return false;
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}
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}
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bool R600VectorRegMerger::tryMergeVector(const RegSeqInfo *Untouched,
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RegSeqInfo *ToMerge, std::vector< std::pair<unsigned, unsigned>> &Remap)
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const {
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unsigned CurrentUndexIdx = 0;
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for (DenseMap<unsigned, unsigned>::iterator It = ToMerge->RegToChan.begin(),
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E = ToMerge->RegToChan.end(); It != E; ++It) {
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DenseMap<unsigned, unsigned>::const_iterator PosInUntouched =
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Untouched->RegToChan.find((*It).first);
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if (PosInUntouched != Untouched->RegToChan.end()) {
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Remap.push_back(std::pair<unsigned, unsigned>
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((*It).second, (*PosInUntouched).second));
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continue;
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}
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if (CurrentUndexIdx >= Untouched->UndefReg.size())
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return false;
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Remap.push_back(std::pair<unsigned, unsigned>
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((*It).second, Untouched->UndefReg[CurrentUndexIdx++]));
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}
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return true;
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}
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static
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unsigned getReassignedChan(
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const std::vector<std::pair<unsigned, unsigned>> &RemapChan,
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unsigned Chan) {
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for (unsigned j = 0, je = RemapChan.size(); j < je; j++) {
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if (RemapChan[j].first == Chan)
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return RemapChan[j].second;
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}
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llvm_unreachable("Chan wasn't reassigned");
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}
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MachineInstr *R600VectorRegMerger::RebuildVector(
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RegSeqInfo *RSI, const RegSeqInfo *BaseRSI,
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const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const {
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Register Reg = RSI->Instr->getOperand(0).getReg();
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MachineBasicBlock::iterator Pos = RSI->Instr;
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MachineBasicBlock &MBB = *Pos->getParent();
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DebugLoc DL = Pos->getDebugLoc();
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Register SrcVec = BaseRSI->Instr->getOperand(0).getReg();
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DenseMap<unsigned, unsigned> UpdatedRegToChan = BaseRSI->RegToChan;
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std::vector<unsigned> UpdatedUndef = BaseRSI->UndefReg;
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for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(),
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E = RSI->RegToChan.end(); It != E; ++It) {
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Register DstReg = MRI->createVirtualRegister(&R600::R600_Reg128RegClass);
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unsigned SubReg = (*It).first;
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unsigned Swizzle = (*It).second;
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unsigned Chan = getReassignedChan(RemapChan, Swizzle);
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MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(R600::INSERT_SUBREG),
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DstReg)
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.addReg(SrcVec)
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.addReg(SubReg)
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.addImm(Chan);
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UpdatedRegToChan[SubReg] = Chan;
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std::vector<unsigned>::iterator ChanPos = llvm::find(UpdatedUndef, Chan);
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if (ChanPos != UpdatedUndef.end())
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UpdatedUndef.erase(ChanPos);
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assert(!is_contained(UpdatedUndef, Chan) &&
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"UpdatedUndef shouldn't contain Chan more than once!");
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LLVM_DEBUG(dbgs() << " ->"; Tmp->dump(););
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(void)Tmp;
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SrcVec = DstReg;
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}
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MachineInstr *NewMI =
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BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec);
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LLVM_DEBUG(dbgs() << " ->"; NewMI->dump(););
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LLVM_DEBUG(dbgs() << " Updating Swizzle:\n");
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for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg),
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E = MRI->use_instr_end(); It != E; ++It) {
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LLVM_DEBUG(dbgs() << " "; (*It).dump(); dbgs() << " ->");
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SwizzleInput(*It, RemapChan);
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LLVM_DEBUG((*It).dump());
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}
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RSI->Instr->eraseFromParent();
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// Update RSI
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RSI->Instr = NewMI;
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RSI->RegToChan = UpdatedRegToChan;
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RSI->UndefReg = UpdatedUndef;
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return NewMI;
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}
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void R600VectorRegMerger::RemoveMI(MachineInstr *MI) {
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for (InstructionSetMap::iterator It = PreviousRegSeqByReg.begin(),
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E = PreviousRegSeqByReg.end(); It != E; ++It) {
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std::vector<MachineInstr *> &MIs = (*It).second;
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MIs.erase(llvm::find(MIs, MI), MIs.end());
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}
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for (InstructionSetMap::iterator It = PreviousRegSeqByUndefCount.begin(),
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E = PreviousRegSeqByUndefCount.end(); It != E; ++It) {
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std::vector<MachineInstr *> &MIs = (*It).second;
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MIs.erase(llvm::find(MIs, MI), MIs.end());
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}
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}
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void R600VectorRegMerger::SwizzleInput(MachineInstr &MI,
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const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const {
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unsigned Offset;
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if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
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Offset = 2;
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else
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Offset = 3;
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for (unsigned i = 0; i < 4; i++) {
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unsigned Swizzle = MI.getOperand(i + Offset).getImm() + 1;
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for (unsigned j = 0, e = RemapChan.size(); j < e; j++) {
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if (RemapChan[j].first == Swizzle) {
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MI.getOperand(i + Offset).setImm(RemapChan[j].second - 1);
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break;
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}
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}
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}
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}
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bool R600VectorRegMerger::areAllUsesSwizzeable(unsigned Reg) const {
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for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg),
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E = MRI->use_instr_end(); It != E; ++It) {
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if (!canSwizzle(*It))
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return false;
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}
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return true;
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}
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bool R600VectorRegMerger::tryMergeUsingCommonSlot(RegSeqInfo &RSI,
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RegSeqInfo &CompatibleRSI,
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std::vector<std::pair<unsigned, unsigned>> &RemapChan) {
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for (MachineInstr::mop_iterator MOp = RSI.Instr->operands_begin(),
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MOE = RSI.Instr->operands_end(); MOp != MOE; ++MOp) {
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if (!MOp->isReg())
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continue;
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if (PreviousRegSeqByReg[MOp->getReg()].empty())
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continue;
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for (MachineInstr *MI : PreviousRegSeqByReg[MOp->getReg()]) {
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CompatibleRSI = PreviousRegSeq[MI];
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if (RSI == CompatibleRSI)
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continue;
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if (tryMergeVector(&CompatibleRSI, &RSI, RemapChan))
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return true;
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}
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}
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return false;
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}
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bool R600VectorRegMerger::tryMergeUsingFreeSlot(RegSeqInfo &RSI,
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RegSeqInfo &CompatibleRSI,
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std::vector<std::pair<unsigned, unsigned>> &RemapChan) {
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unsigned NeededUndefs = 4 - RSI.UndefReg.size();
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if (PreviousRegSeqByUndefCount[NeededUndefs].empty())
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return false;
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std::vector<MachineInstr *> &MIs =
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PreviousRegSeqByUndefCount[NeededUndefs];
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CompatibleRSI = PreviousRegSeq[MIs.back()];
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tryMergeVector(&CompatibleRSI, &RSI, RemapChan);
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return true;
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}
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void R600VectorRegMerger::trackRSI(const RegSeqInfo &RSI) {
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for (DenseMap<unsigned, unsigned>::const_iterator
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It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) {
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PreviousRegSeqByReg[(*It).first].push_back(RSI.Instr);
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}
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PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr);
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PreviousRegSeq[RSI.Instr] = RSI;
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}
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bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
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if (skipFunction(Fn.getFunction()))
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return false;
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const R600Subtarget &ST = Fn.getSubtarget<R600Subtarget>();
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TII = ST.getInstrInfo();
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MRI = &Fn.getRegInfo();
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB) {
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MachineBasicBlock *MB = &*MBB;
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PreviousRegSeq.clear();
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PreviousRegSeqByReg.clear();
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PreviousRegSeqByUndefCount.clear();
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for (MachineBasicBlock::iterator MII = MB->begin(), MIIE = MB->end();
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MII != MIIE; ++MII) {
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MachineInstr &MI = *MII;
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if (MI.getOpcode() != R600::REG_SEQUENCE) {
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if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
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Register Reg = MI.getOperand(1).getReg();
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for (MachineRegisterInfo::def_instr_iterator
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It = MRI->def_instr_begin(Reg), E = MRI->def_instr_end();
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It != E; ++It) {
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RemoveMI(&(*It));
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}
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}
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continue;
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}
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RegSeqInfo RSI(*MRI, &MI);
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// All uses of MI are swizzeable ?
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Register Reg = MI.getOperand(0).getReg();
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if (!areAllUsesSwizzeable(Reg))
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continue;
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LLVM_DEBUG({
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dbgs() << "Trying to optimize ";
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MI.dump();
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});
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RegSeqInfo CandidateRSI;
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std::vector<std::pair<unsigned, unsigned>> RemapChan;
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LLVM_DEBUG(dbgs() << "Using common slots...\n";);
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if (tryMergeUsingCommonSlot(RSI, CandidateRSI, RemapChan)) {
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// Remove CandidateRSI mapping
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RemoveMI(CandidateRSI.Instr);
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MII = RebuildVector(&RSI, &CandidateRSI, RemapChan);
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trackRSI(RSI);
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continue;
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}
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LLVM_DEBUG(dbgs() << "Using free slots...\n";);
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RemapChan.clear();
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if (tryMergeUsingFreeSlot(RSI, CandidateRSI, RemapChan)) {
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RemoveMI(CandidateRSI.Instr);
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MII = RebuildVector(&RSI, &CandidateRSI, RemapChan);
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trackRSI(RSI);
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continue;
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}
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//Failed to merge
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trackRSI(RSI);
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}
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}
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return false;
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}
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llvm::FunctionPass *llvm::createR600VectorRegMerger() {
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return new R600VectorRegMerger();
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}
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