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9a4c805887
When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. This patch is for STWU/STWUX (IIC_LdStStoreUpd ) for P8. Since there are already multiple IIC for store update, this patch also merge IIC_LdStSTDU/IIC_LdStStoreUpd to IIC_LdStSTU IIC_LdStSTDUX to IIC_LdStSTUX and we add a new testcase in https://reviews.llvm.org/D54699 to show the difference. Differential Revision: https://reviews.llvm.org/D54700 llvm-svn: 347311
130 lines
7.1 KiB
TableGen
130 lines
7.1 KiB
TableGen
//===-- PPCScheduleG5.td - PPC G5 Scheduling Definitions ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the G5 (970) processor.
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//
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//===----------------------------------------------------------------------===//
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def G5_BPU : FuncUnit; // Branch unit
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def G5_SLU : FuncUnit; // Store/load unit
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def G5_SRU : FuncUnit; // special register unit
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def G5_IU1 : FuncUnit; // integer unit 1 (simple)
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def G5_IU2 : FuncUnit; // integer unit 2 (complex)
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def G5_FPU1 : FuncUnit; // floating point unit 1
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def G5_FPU2 : FuncUnit; // floating point unit 2
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def G5_VPU : FuncUnit; // vector permutation unit
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def G5_VIU1 : FuncUnit; // vector integer unit 1 (simple)
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def G5_VIU2 : FuncUnit; // vector integer unit 2 (complex)
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def G5_VFPU : FuncUnit; // vector floating point unit
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def G5Itineraries : ProcessorItineraries<
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[G5_IU1, G5_IU2, G5_SLU, G5_BPU, G5_FPU1, G5_FPU2,
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G5_VFPU, G5_VIU1, G5_VIU2, G5_VPU], [], [
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InstrItinData<IIC_IntSimple , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntGeneral , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntCompare , [InstrStage<3, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntDivD , [InstrStage<68, [G5_IU1]>]>,
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InstrItinData<IIC_IntDivW , [InstrStage<36, [G5_IU1]>]>,
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InstrItinData<IIC_IntMFFS , [InstrStage<6, [G5_IU2]>]>,
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InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G5_VFPU]>]>,
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InstrItinData<IIC_IntMTFSB0 , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_IntMulHD , [InstrStage<7, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntMulHW , [InstrStage<5, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntMulHWU , [InstrStage<5, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntMulLI , [InstrStage<4, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntRFID , [InstrStage<1, [G5_IU2]>]>,
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InstrItinData<IIC_IntRotateD , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntRotateDI , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntRotate , [InstrStage<4, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntShift , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntTrapD , [InstrStage<1, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_IntTrapW , [InstrStage<1, [G5_IU1, G5_IU2]>]>,
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InstrItinData<IIC_BrB , [InstrStage<1, [G5_BPU]>]>,
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InstrItinData<IIC_BrCR , [InstrStage<4, [G5_BPU]>]>,
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InstrItinData<IIC_BrMCR , [InstrStage<2, [G5_BPU]>]>,
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InstrItinData<IIC_BrMCRX , [InstrStage<3, [G5_BPU]>]>,
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InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLoad , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStStore , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStDSS , [InstrStage<10, [G5_SLU]>]>,
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InstrItinData<IIC_LdStICBI , [InstrStage<40, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTFD , [InstrStage<4, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTFDU , [InstrStage<4, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLD , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLDU , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLDUX , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLDARX , [InstrStage<11, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLFD , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLFDU , [InstrStage<5, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLFDUX , [InstrStage<5, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLHA , [InstrStage<5, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLHAU , [InstrStage<5, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLHAUX , [InstrStage<5, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLMW , [InstrStage<64, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLWA , [InstrStage<5, [G5_SLU]>]>,
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InstrItinData<IIC_LdStLWARX , [InstrStage<11, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSLBIA , [InstrStage<40, [G5_SLU]>]>, // needs work
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InstrItinData<IIC_LdStSLBIE , [InstrStage<2, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTD , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTU , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTUX , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTDCX , [InstrStage<11, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTVEBX , [InstrStage<5, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSTWCX , [InstrStage<11, [G5_SLU]>]>,
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InstrItinData<IIC_LdStSync , [InstrStage<35, [G5_SLU]>]>,
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InstrItinData<IIC_SprISYNC , [InstrStage<40, [G5_SLU]>]>, // needs work
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InstrItinData<IIC_SprMFSR , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_SprMTMSR , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_SprMTSR , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G5_SLU]>]>,
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InstrItinData<IIC_SprMFCR , [InstrStage<2, [G5_IU2]>]>,
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InstrItinData<IIC_SprMFCRF , [InstrStage<2, [G5_IU2]>]>,
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InstrItinData<IIC_SprMFMSR , [InstrStage<3, [G5_IU2]>]>,
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InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G5_IU2]>]>,
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InstrItinData<IIC_SprMFTB , [InstrStage<10, [G5_IU2]>]>,
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InstrItinData<IIC_SprMTSPR , [InstrStage<8, [G5_IU2]>]>,
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InstrItinData<IIC_SprSC , [InstrStage<1, [G5_IU2]>]>,
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InstrItinData<IIC_FPGeneral , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPAddSub , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPCompare , [InstrStage<8, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPDivD , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPDivS , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPFused , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPRes , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPSqrtD , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_FPSqrtS , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>,
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InstrItinData<IIC_VecGeneral , [InstrStage<2, [G5_VIU1]>]>,
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InstrItinData<IIC_VecFP , [InstrStage<8, [G5_VFPU]>]>,
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InstrItinData<IIC_VecFPCompare, [InstrStage<2, [G5_VFPU]>]>,
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InstrItinData<IIC_VecComplex , [InstrStage<5, [G5_VIU2]>]>,
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InstrItinData<IIC_VecPerm , [InstrStage<3, [G5_VPU]>]>,
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InstrItinData<IIC_VecFPRound , [InstrStage<8, [G5_VFPU]>]>,
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InstrItinData<IIC_VecVSL , [InstrStage<2, [G5_VIU1]>]>,
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InstrItinData<IIC_VecVSR , [InstrStage<3, [G5_VPU]>]>
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]>;
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// ===---------------------------------------------------------------------===//
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// G5 machine model for scheduling and other instruction cost heuristics.
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def G5Model : SchedMachineModel {
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let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle.
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let LoadLatency = 3; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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// Itineraries are queried instead.
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let MispredictPenalty = 16;
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let CompleteModel = 0;
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let Itineraries = G5Itineraries;
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}
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