mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-21 12:02:58 +02:00
f8cb784f68
Post-RA sched strategy and scheduling instruction annotations for z196, zEC12 and z13. This scheduler optimizes decoder grouping and balances processor resources (including side steering the FPd unit instructions). The SystemZHazardRecognizer keeps track of the scheduling state, which can be dumped with -debug-only=misched. Reviers: Ulrich Weigand, Andrew Trick. https://reviews.llvm.org/D17260 llvm-svn: 284704
69 lines
2.5 KiB
TableGen
69 lines
2.5 KiB
TableGen
//===-- SystemZ.td - Describe the SystemZ target machine -----*- tblgen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Target-independent interfaces which we are implementing
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "llvm/Target/Target.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SystemZ subtargets scheduling models.
|
|
//===----------------------------------------------------------------------===//
|
|
include "SystemZSchedule.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SystemZ supported processors and features
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "SystemZProcessors.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register file description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "SystemZRegisterInfo.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Calling convention description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "SystemZCallingConv.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction descriptions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "SystemZOperators.td"
|
|
include "SystemZOperands.td"
|
|
include "SystemZPatterns.td"
|
|
include "SystemZInstrFormats.td"
|
|
include "SystemZInstrInfo.td"
|
|
include "SystemZInstrVector.td"
|
|
include "SystemZInstrFP.td"
|
|
|
|
def SystemZInstrInfo : InstrInfo {}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembly parser
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def SystemZAsmParser : AsmParser {
|
|
let ShouldEmitMatchRegisterName = 0;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Top-level target declaration
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def SystemZ : Target {
|
|
let InstructionSet = SystemZInstrInfo;
|
|
let AssemblyParsers = [SystemZAsmParser];
|
|
}
|