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llvm-mirror/test/CodeGen/AArch64/machine-sink-zr.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

44 lines
838 B
YAML

# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-sink -o - %s | FileCheck %s
--- |
define void @sinkwzr() { ret void }
...
---
name: sinkwzr
tracksRegLiveness: true
registers:
- { id: 0, class: gpr32 }
- { id: 1, class: gpr32 }
- { id: 2, class: gpr32sp }
- { id: 3, class: gpr32 }
- { id: 4, class: gpr32 }
body: |
; Check that WZR copy is sunk into the loop preheader.
; CHECK-LABEL: name: sinkwzr
; CHECK-LABEL: bb.0:
; CHECK-NOT: COPY $wzr
bb.0:
liveins: $w0
%0 = COPY $w0
%1 = COPY $wzr
CBZW %0, %bb.3
; CHECK-LABEL: bb.1:
; CHECK: COPY $wzr
bb.1:
B %bb.2
bb.2:
%2 = PHI %0, %bb.1, %4, %bb.2
$w0 = COPY %1
%3 = SUBSWri %2, 1, 0, implicit-def dead $nzcv
%4 = COPY %3
CBZW %3, %bb.3
B %bb.2
bb.3:
RET_ReallyLR
...