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llvm-mirror/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil. 
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

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# RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: cluster_add_addc
# GCN: S_NOP 0, implicit-def $vcc
# GCN: dead %2:vgpr_32, %3:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit $exec
# GCN: dead %4:vgpr_32, dead %5:sreg_64_xexec = V_ADDC_U32_e64 %6, %7, %3, implicit $exec
name: cluster_add_addc
registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- { id: 5, class: sreg_64_xexec }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
body: |
bb.0:
%0 = V_MOV_B32_e32 0, implicit $exec
%1 = V_MOV_B32_e32 0, implicit $exec
%2, %3 = V_ADD_I32_e64 %0, %1, implicit $exec
%6 = V_MOV_B32_e32 0, implicit $exec
%7 = V_MOV_B32_e32 0, implicit $exec
S_NOP 0, implicit def $vcc
%4, %5 = V_ADDC_U32_e64 %6, %7, %3, implicit $exec
...
# GCN-LABEL: name: interleave_add64s
# GCN: dead %8:vgpr_32, %9:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit $exec
# GCN-NEXT: dead %12:vgpr_32, dead %13:sreg_64_xexec = V_ADDC_U32_e64 %4, %5, %9, implicit $exec
# GCN-NEXT: dead %10:vgpr_32, %11:sreg_64_xexec = V_ADD_I32_e64 %2, %3, implicit $exec
# GCN-NEXT: dead %14:vgpr_32, dead %15:sreg_64_xexec = V_ADDC_U32_e64 %6, %7, %11, implicit $exec
name: interleave_add64s
registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: vgpr_32 }
- { id: 4, class: vgpr_32 }
- { id: 5, class: vgpr_32 }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
- { id: 8, class: vgpr_32 }
- { id: 9, class: sreg_64_xexec }
- { id: 10, class: vgpr_32 }
- { id: 11, class: sreg_64_xexec }
- { id: 12, class: vgpr_32 }
- { id: 13, class: sreg_64_xexec }
- { id: 14, class: vgpr_32 }
- { id: 15, class: sreg_64_xexec }
body: |
bb.0:
%0 = V_MOV_B32_e32 0, implicit $exec
%1 = V_MOV_B32_e32 0, implicit $exec
%2 = V_MOV_B32_e32 0, implicit $exec
%3 = V_MOV_B32_e32 0, implicit $exec
%4 = V_MOV_B32_e32 0, implicit $exec
%5 = V_MOV_B32_e32 0, implicit $exec
%6 = V_MOV_B32_e32 0, implicit $exec
%7 = V_MOV_B32_e32 0, implicit $exec
%8, %9 = V_ADD_I32_e64 %0, %1, implicit $exec
%10, %11 = V_ADD_I32_e64 %2, %3, implicit $exec
%12, %13 = V_ADDC_U32_e64 %4, %5, %9, implicit $exec
%14, %15 = V_ADDC_U32_e64 %6, %7, %11, implicit $exec
...
# GCN-LABEL: name: cluster_mov_addc
# GCN: S_NOP 0, implicit-def $vcc
# GCN-NEXT: %2:sreg_64_xexec = S_MOV_B64 0
# GCN-NEXT: dead %3:vgpr_32, dead %4:sreg_64_xexec = V_ADDC_U32_e64 %0, %1, %2, implicit $exec
name: cluster_mov_addc
registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: sreg_64_xexec }
- { id: 3, class: vgpr_32 }
- { id: 4, class: sreg_64_xexec }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
body: |
bb.0:
%0 = V_MOV_B32_e32 0, implicit $exec
%1 = V_MOV_B32_e32 0, implicit $exec
%2 = S_MOV_B64 0
S_NOP 0, implicit def $vcc
%3, %4 = V_ADDC_U32_e64 %0, %1, %2, implicit $exec
...
# GCN-LABEL: name: no_cluster_add_addc_diff_sgpr
# GCN: dead %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit $exec
# GCN-NEXT: %6:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
# GCN-NEXT: %7:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
# GCN-NEXT: S_NOP 0, implicit-def $vcc
# GCN-NEXT: %8:sreg_64_xexec = S_MOV_B64 0
# GCN-NEXT: dead %4:vgpr_32, dead %5:sreg_64_xexec = V_ADDC_U32_e64 %6, %7, %8, implicit $exec
name: no_cluster_add_addc_diff_sgpr
registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- { id: 5, class: sreg_64_xexec }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
- { id: 8, class: sreg_64_xexec }
body: |
bb.0:
%0 = V_MOV_B32_e32 0, implicit $exec
%1 = V_MOV_B32_e32 0, implicit $exec
%8 = S_MOV_B64 0
%2, %3 = V_ADD_I32_e64 %0, %1, implicit $exec
%6 = V_MOV_B32_e32 0, implicit $exec
%7 = V_MOV_B32_e32 0, implicit $exec
S_NOP 0, implicit def $vcc
%4, %5 = V_ADDC_U32_e64 %6, %7, %8, implicit $exec
...
# GCN-LABEL: name: cluster_sub_subb
# GCN: S_NOP 0, implicit-def $vcc
# GCN: dead %2:vgpr_32, %3:sreg_64_xexec = V_SUB_I32_e64 %0, %1, implicit $exec
# GCN: dead %4:vgpr_32, dead %5:sreg_64_xexec = V_SUBB_U32_e64 %6, %7, %3, implicit $exec
name: cluster_sub_subb
registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- { id: 5, class: sreg_64_xexec }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
body: |
bb.0:
%0 = V_MOV_B32_e32 0, implicit $exec
%1 = V_MOV_B32_e32 0, implicit $exec
%2, %3 = V_SUB_I32_e64 %0, %1, implicit $exec
%6 = V_MOV_B32_e32 0, implicit $exec
%7 = V_MOV_B32_e32 0, implicit $exec
S_NOP 0, implicit def $vcc
%4, %5 = V_SUBB_U32_e64 %6, %7, %3, implicit $exec
...
# GCN-LABEL: name: cluster_cmp_cndmask
# GCN: S_NOP 0, implicit-def $vcc
# GCN-NEXT: %3:sreg_64_xexec = V_CMP_EQ_I32_e64 %0, %1, implicit $exec
# GCN-NEXT: dead %4:vgpr_32 = V_CNDMASK_B32_e64 %0, %1, %3, implicit $exec
name: cluster_cmp_cndmask
registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- { id: 5, class: sreg_64_xexec }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
body: |
bb.0:
%0 = V_MOV_B32_e32 0, implicit $exec
%1 = V_MOV_B32_e32 0, implicit $exec
%3 = V_CMP_EQ_I32_e64 %0, %1, implicit $exec
S_NOP 0, implicit def $vcc
%4 = V_CNDMASK_B32_e64 %0, %1, %3, implicit $exec
...
# GCN-LABEL: name: cluster_multi_use_cmp_cndmask
# GCN: %4:sreg_64_xexec = V_CMP_EQ_I32_e64 %0, %1, implicit $exec
# GCN-NEXT: dead %5:vgpr_32 = V_CNDMASK_B32_e64 %2, %1, %4, implicit $exec
# GCN-NEXT: dead %6:vgpr_32 = V_CNDMASK_B32_e64 %1, %3, %4, implicit $exec
name: cluster_multi_use_cmp_cndmask
registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: vgpr_32 }
- { id: 4, class: sreg_64_xexec }
- { id: 5, class: vgpr_32 }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
body: |
bb.0:
%0 = V_MOV_B32_e32 0, implicit $exec
%1 = V_MOV_B32_e32 0, implicit $exec
%2 = V_MOV_B32_e32 0, implicit $exec
%3 = V_MOV_B32_e32 0, implicit $exec
%4 = V_CMP_EQ_I32_e64 %0, %1, implicit $exec
S_NOP 0, implicit def $vcc
%5 = V_CNDMASK_B32_e64 %2, %1, %4, implicit $exec
%6 = V_CNDMASK_B32_e64 %1, %3, %4, implicit $exec
...
# GCN-LABEL: name: cluster_multi_use_cmp_cndmask2
# GCN: %4:sreg_64_xexec = V_CMP_EQ_I32_e64 %0, %1, implicit $exec
# GCN-NEXT: dead %5:vgpr_32 = V_CNDMASK_B32_e64 %2, %1, %4, implicit $exec
# GCN-NEXT: %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
# GCN-NEXT: dead %6:vgpr_32 = V_CNDMASK_B32_e64 %1, %3, %4, implicit $exec
name: cluster_multi_use_cmp_cndmask2
registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: vgpr_32 }
- { id: 4, class: sreg_64_xexec }
- { id: 5, class: vgpr_32 }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
body: |
bb.0:
%0 = V_MOV_B32_e32 0, implicit $exec
%1 = V_MOV_B32_e32 0, implicit $exec
%4 = V_CMP_EQ_I32_e64 %0, %1, implicit $exec
%2 = V_MOV_B32_e32 0, implicit $exec
%5 = V_CNDMASK_B32_e64 %2, %1, %4, implicit $exec
%3 = V_MOV_B32_e32 0, implicit $exec
%6 = V_CNDMASK_B32_e64 %1, %3, %4, implicit $exec
...
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