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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
124 lines
3.5 KiB
YAML
124 lines
3.5 KiB
YAML
#RUN: llc -run-pass arm-cp-islands %s -o - | FileCheck %s
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--- |
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; ModuleID = 'test.ll'
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source_filename = "test.c"
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8r-arm-none-eabi"
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define void @Func(i32 %i, i32* nocapture %p) local_unnamed_addr {
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entry:
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switch i32 %i, label %sw.epilog [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 2, label %sw.epilog.sink.split
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i32 4, label %sw.bb3
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]
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sw.bb: ; preds = %entry
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br label %sw.epilog.sink.split
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sw.bb1: ; preds = %entry
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store i32 0, i32* %p, align 4
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br label %sw.epilog.sink.split
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sw.bb3: ; preds = %entry
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br label %sw.epilog.sink.split
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sw.epilog.sink.split: ; preds = %sw.bb3, %sw.bb1, %sw.bb, %entry
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%.sink = phi i32 [ 2, %sw.bb3 ], [ 0, %sw.bb ], [ 1, %entry ], [ 1, %sw.bb1 ]
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store i32 %.sink, i32* %p, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.epilog.sink.split, %entry
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ret void
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}
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...
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---
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name: Func
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$r0' }
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- { reg: '$r1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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jumpTable:
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kind: inline
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entries:
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- id: 0
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blocks: [ '%bb.2.sw.bb', '%bb.3.sw.bb1', '%bb.5.sw.epilog.sink.split',
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'%bb.6.sw.epilog', '%bb.4.sw.bb3' ]
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# The ADD should be deleted along with the LEA
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# CHECK-NOT: t2LEApcrelJT
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# CHECK-NOT: t2ADDrs
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# CHECK: tMOVi8
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# CHECK: t2TBB_JT
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body: |
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bb.0.entry:
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successors: %bb.6.sw.epilog(0x0ccccccb), %bb.1.entry(0x73333335)
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liveins: $r0, $r1
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tCMPi8 $r0, 4, 14, $noreg, implicit-def $cpsr
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t2Bcc %bb.6.sw.epilog, 8, killed $cpsr
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bb.1.entry:
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successors: %bb.2.sw.bb(0x1c71c71c), %bb.3.sw.bb1(0x1c71c71c), %bb.5.sw.epilog.sink.split(0x1c71c71c), %bb.6.sw.epilog(0x0e38e38e), %bb.4.sw.bb3(0x1c71c71c)
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liveins: $r0, $r1
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$r2 = t2LEApcrelJT %jump-table.0, 14, $noreg
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$r3 = t2ADDrs killed $r2, $r0, 18, 14, $noreg, $noreg
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$r2, dead $cpsr = tMOVi8 1, 14, $noreg
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t2BR_JT killed $r3, killed $r0, %jump-table.0
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bb.2.sw.bb:
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successors: %bb.5.sw.epilog.sink.split(0x80000000)
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liveins: $r1
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$r2, dead $cpsr = tMOVi8 0, 14, $noreg
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t2B %bb.5.sw.epilog.sink.split, 14, $noreg
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bb.3.sw.bb1:
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successors: %bb.5.sw.epilog.sink.split(0x80000000)
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liveins: $r1
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$r0, dead $cpsr = tMOVi8 0, 14, $noreg
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$r2, dead $cpsr = tMOVi8 1, 14, $noreg
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tSTRi killed $r0, $r1, 0, 14, $noreg :: (store 4 into %ir.p)
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t2B %bb.5.sw.epilog.sink.split, 14, $noreg
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bb.4.sw.bb3:
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successors: %bb.5.sw.epilog.sink.split(0x80000000)
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liveins: $r1
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$r2, dead $cpsr = tMOVi8 2, 14, $noreg
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bb.5.sw.epilog.sink.split:
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successors: %bb.6.sw.epilog(0x80000000)
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liveins: $r1, $r2
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tSTRi killed $r2, killed $r1, 0, 14, $noreg :: (store 4 into %ir.p)
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bb.6.sw.epilog:
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tBX_RET 14, $noreg
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...
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