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2af1dc95bf
Summary: Previously we lowered it literally, to shifts and xors. Reviewers: tra Subscribers: jholewinski, llvm-commits Differential Revision: https://reviews.llvm.org/D28722 llvm-svn: 292303
32 lines
758 B
LLVM
32 lines
758 B
LLVM
; Check that various LLVM idioms get lowered to NVPTX as expected.
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
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; CHECK-LABEL: abs_i16(
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define i16 @abs_i16(i16 %a) {
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; CHECK: abs.s16
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%neg = sub i16 0, %a
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%abs.cond = icmp sge i16 %a, 0
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%abs = select i1 %abs.cond, i16 %a, i16 %neg
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ret i16 %abs
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}
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; CHECK-LABEL: abs_i32(
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define i32 @abs_i32(i32 %a) {
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; CHECK: abs.s32
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%neg = sub i32 0, %a
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%abs.cond = icmp sge i32 %a, 0
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%abs = select i1 %abs.cond, i32 %a, i32 %neg
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ret i32 %abs
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}
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; CHECK-LABEL: abs_i64(
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define i64 @abs_i64(i64 %a) {
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; CHECK: abs.s64
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%neg = sub i64 0, %a
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%abs.cond = icmp sge i64 %a, 0
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%abs = select i1 %abs.cond, i64 %a, i64 %neg
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ret i64 %abs
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}
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