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813af3fadc
This commit verifies that the parsed machine instructions contain the implicit register operands as specified by the MCInstrDesc. Variadic and call instructions aren't verified. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10781 llvm-svn: 241537
24 lines
489 B
YAML
24 lines
489 B
YAML
# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
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# This test ensures that the MIR parser parses X86 registers correctly.
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--- |
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define i32 @foo() {
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entry:
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ret i32 0
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}
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...
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---
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# CHECK: name: foo
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name: foo
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body:
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- id: 0
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name: entry
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instructions:
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# CHECK: - '%eax = MOV32r0
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# CHECK-NEXT: - 'RETQ %eax
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- '%eax = MOV32r0 implicit-def %eflags'
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- 'RETQ %eax'
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...
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