Andrea Di Biagio b770dd344e [X86] Improved lowering of v4x32 build_vector dag nodes. ... This patch improves the lowering of v4f32 and v4i32 build_vector dag nodes that are known to have at least two non-zero elements. With this patch, a build_vector that performs a blend with zero is converted into a shuffle. This is done to let the shuffle legalizer expand the dag node in a optimal way. For example, if we know that a build_vector performs a blend with zero, we can try to lower it as a movq/blend instead of always selecting an insertps. This patch also improves the logic that lowers a build_vector into a insertps with zero masking. See for example the extra test cases added to test sse41.ll. Differential Revision: http://reviews.llvm.org/D6311 llvm-svn: 222375		2014-11-19 19:34:29 +00:00
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AArch64	[AArch64] Enable SeparateConstOffsetFromGEP, EarlyCSE and LICM passes on AArch64 backend.	2014-11-19 06:39:53 +00:00
ARM	Fix ARM triple parsing	2014-11-17 14:08:57 +00:00
CPP
Generic
Hexagon	Handle ctor/init_array initialization.	2014-11-03 14:56:05 +00:00
Inputs
Mips	[mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2.	2014-11-19 13:23:58 +00:00
MSP430
NVPTX	[NVPTX] Add NVPTXLowerStructArgs pass	2014-11-05 18:19:30 +00:00
PowerPC	[PowerPC] Add VSX builtins for vec_div	2014-11-14 12:10:40 +00:00
R600	R600/SI: Make SIInstrInfo::isOperandLegal() more strict	2014-11-19 16:58:49 +00:00
SPARC
SystemZ
Thumb	[Thumb1] Re-write emitThumbRegPlusImmediate	2014-11-17 11:18:10 +00:00
Thumb2	ARM: allow constpool entry to be moved to the user's block in all cases.	2014-11-13 17:58:53 +00:00
X86	[X86] Improved lowering of v4x32 build_vector dag nodes.	2014-11-19 19:34:29 +00:00
XCore	Fix a bit of confusion about .set and produce more readable assembly.	2014-10-21 01:17:30 +00:00