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llvm-mirror/test/CodeGen/X86/extractelement-legalization-cycle.ll
Robert Lougher 68f61ad534 Fix cycle in selection DAG introduced by extractelement legalization
During selection DAG legalization, extractelement is replaced with a load
instruction.  To do this, a temporary store to the stack is used unless an
existing store is found that can be re-used.
    
If re-using a store, the chain going out of the store must be replaced by
the one going out of the new load (this ensures that any stores that must
take place after the store happens after the load, else the value might
be overwritten before it is loaded).
    
The problem is, if the extractelement index is dependent on the store
replacing the chain will introduce a cycle in the selection DAG (the load
uses the index, and by replacing the chain we will make the index dependent
on the load).
    
To fix this, if the index is dependent on the store, the store is skipped.
This is conservative as we may end up creating an unnecessary extra store
to the stack.  However, the situation is not expected to occur very often.

Differential Revision: http://reviews.llvm.org/D15330

llvm-svn: 255114
2015-12-09 14:34:10 +00:00

22 lines
899 B
LLVM

; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; When the extractelement is converted to a load the store can be re-used.
; This will, however, introduce a cycle into the selection DAG (the load
; of the extractelement index is dependent on the store, and so after the
; conversion it becomes dependent on the new load, which is dependent on
; the index). Make sure we skip the store, and conservatively instead
; use a store to the stack.
define float @foo(i32* %i, <4 x float>* %v) {
; CHECK-LABEL: foo:
; CHECK: movaps %xmm0, -[[OFFSET:[0-9]+]](%rsp)
; CHECK: movss -[[OFFSET]](%rsp,{{.*}}), %xmm0 {{.*}}
; CHECK-NEXT: retq
%1 = load <4 x float>, <4 x float>* %v, align 16
%mul = fmul <4 x float> %1, %1
store <4 x float> %mul, <4 x float>* %v, align 16
%2 = load i32, i32* %i, align 4
%vecext = extractelement <4 x float> %mul, i32 %2
ret float %vecext
}