Jessica Paquette 3fcc23c823 [GlobalISel] Add G_ASSERT_ZEXT ... This adds a generic opcode which communicates that a type has already been zero-extended from a narrower type. This is intended to be similar to AssertZext in SelectionDAG. For example, ``` %x_was_extended:_(s64) = G_ASSERT_ZEXT %x, 16 ``` Signifies that the top 48 bits of %x are known to be 0. This is useful in cases like this: ``` define i1 @zeroext_param(i8 zeroext %x) { %cmp = icmp ult i8 %x, -20 ret i1 %cmp } ``` In AArch64, `%x` must use a 32-bit register, which is then truncated to a 8-bit value. If we know that `%x` is already zero-ed out in the relevant high bits, we can avoid the truncate. Currently, in GISel, this looks like this: ``` _zeroext_param: and w8, w0, #0xff ; We don't actually need this! cmp w8, #236 cset w0, lo ret ``` While SDAG does not produce the truncation, since it knows that it's unnecessary: ``` _zeroext_param: cmp w0, #236 cset w0, lo ret ``` This patch - Adds G_ASSERT_ZEXT - Adds MIRBuilder support for it - Adds MachineVerifier support for it - Documents it It also puts G_ASSERT_ZEXT into its own class of "hint instruction." (There should be a G_ASSERT_SEXT in the future, maybe a G_ASSERT_ALIGN as well.) This allows us to skip over hints in the legalizer etc. These can then later be selected like COPY instructions or removed. Differential Revision: https://reviews.llvm.org/D95564		2021-01-28 13:58:37 -08:00
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block-extract.png	[globalisel][docs] Add a section about debugging with the block extractor	2019-11-05 14:48:27 -08:00
GenericOpcode.rst	[GlobalISel] Add G_ASSERT_ZEXT	2021-01-28 13:58:37 -08:00
GMIR.rst	[docs] Fix typos	2020-08-09 19:31:49 -07:00
index.rst	[globalisel][docs] Rework GMIR documentation and add an early GenericOpcode reference	2019-11-05 15:16:43 -08:00
InstructionSelect.rst
IRTranslator.rst	Update references to 'master' branch.	2020-12-21 19:10:34 +00:00
KnownBits.rst	Doc: Links should use https	2020-03-22 22:49:33 +01:00
Legalizer.rst	GlobalISel: Make type for lower action more consistently optional	2020-08-17 16:24:55 -04:00
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pipeline-overview-with-combiners.png
pipeline-overview.png
Pipeline.rst	Try to fix sphinx "Could not lex literal_block as "llvm"" warning.	2019-11-09 22:15:26 +00:00
Porting.rst	[globalisel][docs] Add the tutorial to the Porting document	2019-10-30 14:53:39 -07:00
RegBankSelect.rst
Resources.rst
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