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https://github.com/RPCS3/llvm-mirror.git
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46cdf3f128
Currently the MIR framework prints all its outputs (errors and actual representation) on stderr. This patch fixes that by printing the regular output in the output specified with -o. Differential Revision: http://reviews.llvm.org/D22251 llvm-svn: 275314
93 lines
2.6 KiB
YAML
93 lines
2.6 KiB
YAML
# RUN: llc -start-after=dead-mi-elimination -stop-after=twoaddressinstruction -o - %s | FileCheck %s
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--- |
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@d = global i32 15, align 4
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@b = global i32* @d, align 8
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@a = common global i32 0, align 4
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; Function Attrs: nounwind
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define signext i32 @main() #0 {
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entry:
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%0 = load i32*, i32** @b, align 8
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%1 = load i32, i32* @a, align 4
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%lnot = icmp eq i32 %1, 0
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%lnot.ext = zext i1 %lnot to i32
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%shr.i = lshr i32 2072, %lnot.ext
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%call.lobit = lshr i32 %shr.i, 7
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%2 = and i32 %call.lobit, 1
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%3 = load i32, i32* %0, align 4
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%or = or i32 %2, %3
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store i32 %or, i32* %0, align 4
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%4 = load i32, i32* @a, align 4
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%lnot.1 = icmp eq i32 %4, 0
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%lnot.ext.1 = zext i1 %lnot.1 to i32
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%shr.i.1 = lshr i32 2072, %lnot.ext.1
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%call.lobit.1 = lshr i32 %shr.i.1, 7
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%5 = and i32 %call.lobit.1, 1
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%or.1 = or i32 %5, %or
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store i32 %or.1, i32* %0, align 4
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ret i32 %or.1
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}
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attributes #0 = { nounwind "target-cpu"="ppc64" }
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...
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---
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name: main
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alignment: 2
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exposesReturnsTwice: false
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hasInlineAsm: false
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isSSA: true
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tracksRegLiveness: true
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tracksSubRegLiveness: false
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registers:
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- { id: 0, class: g8rc_and_g8rc_nox0 }
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- { id: 1, class: g8rc_and_g8rc_nox0 }
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- { id: 2, class: gprc }
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- { id: 3, class: gprc }
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- { id: 4, class: gprc }
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- { id: 5, class: g8rc_and_g8rc_nox0 }
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- { id: 6, class: g8rc_and_g8rc_nox0 }
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- { id: 7, class: gprc }
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- { id: 8, class: gprc }
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- { id: 9, class: gprc }
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- { id: 10, class: g8rc }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0.entry:
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liveins: %x2
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%0 = ADDIStocHA %x2, @b
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%1 = LD target-flags(ppc-toc-lo) @b, killed %0 :: (load 8 from @b)
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%2 = LWZ 0, %1 :: (load 4 from %ir.0)
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%3 = LI 0
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%4 = RLWIMI %3, killed %2, 0, 0, 31
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; CHECK-LABEL: name: main
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; CHECK: %[[REG1:[0-9]+]] = LI 0
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; CHECK: %[[REG2:[0-9]+]] = COPY %[[REG1]]
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; CHECK: %[[REG2]] = RLWIMI %[[REG2]], killed %2, 0, 0, 31
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%8 = RLWIMI %3, %4, 0, 0, 31
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STW %4, 0, %1 :: (store 4 into %ir.0)
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%10 = EXTSW_32_64 %8
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STW %8, 0, %1 :: (store 4 into %ir.0)
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%x3 = COPY %10
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BLR8 implicit %x3, implicit %lr8, implicit %rm
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...
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