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f0ca422f64
autogenerated. Also update existing test cases which appear to be generated by it and weren't modified (other than addition of the header) by rerunning it. llvm-svn: 253917
91 lines
2.6 KiB
LLVM
91 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-slow-unaligned-mem-16 | FileCheck %s --check-prefix=FAST
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+slow-unaligned-mem-16 | FileCheck %s --check-prefix=SLOW
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; Verify that the DAGCombiner is creating unaligned 16-byte loads and stores
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; if and only if those are fast.
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define void @merge_const_vec_store(i64* %ptr) {
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; FAST-LABEL: merge_const_vec_store:
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; FAST: # BB#0:
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; FAST-NEXT: xorps %xmm0, %xmm0
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; FAST-NEXT: movups %xmm0, (%rdi)
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; FAST-NEXT: retq
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;
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; SLOW-LABEL: merge_const_vec_store:
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; SLOW: # BB#0:
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; SLOW-NEXT: movq $0, (%rdi)
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; SLOW-NEXT: movq $0, 8(%rdi)
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; SLOW-NEXT: retq
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%idx0 = getelementptr i64, i64* %ptr, i64 0
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%idx1 = getelementptr i64, i64* %ptr, i64 1
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store i64 0, i64* %idx0, align 8
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store i64 0, i64* %idx1, align 8
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ret void
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}
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define void @merge_vec_element_store(<4 x double> %v, double* %ptr) {
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; FAST-LABEL: merge_vec_element_store:
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; FAST: # BB#0:
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; FAST-NEXT: movups %xmm0, (%rdi)
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; FAST-NEXT: retq
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;
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; SLOW-LABEL: merge_vec_element_store:
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; SLOW: # BB#0:
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; SLOW-NEXT: movlpd %xmm0, (%rdi)
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; SLOW-NEXT: movhpd %xmm0, 8(%rdi)
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; SLOW-NEXT: retq
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%vecext0 = extractelement <4 x double> %v, i32 0
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%vecext1 = extractelement <4 x double> %v, i32 1
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%idx0 = getelementptr double, double* %ptr, i64 0
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%idx1 = getelementptr double, double* %ptr, i64 1
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store double %vecext0, double* %idx0, align 8
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store double %vecext1, double* %idx1, align 8
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ret void
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}
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;; TODO: FAST *should* be:
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;; movups (%rdi), %xmm0
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;; movups %xmm0, 40(%rdi)
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;; ..but is not currently. See the UseAA FIXME in DAGCombiner.cpp
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;; visitSTORE.
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define void @merge_vec_load_and_stores(i64 *%ptr) {
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; FAST-LABEL: merge_vec_load_and_stores:
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; FAST: # BB#0:
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; FAST-NEXT: movq (%rdi), %rax
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; FAST-NEXT: movq 8(%rdi), %rcx
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; FAST-NEXT: movq %rax, 40(%rdi)
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; FAST-NEXT: movq %rcx, 48(%rdi)
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; FAST-NEXT: retq
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;
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; SLOW-LABEL: merge_vec_load_and_stores:
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; SLOW: # BB#0:
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; SLOW-NEXT: movq (%rdi), %rax
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; SLOW-NEXT: movq 8(%rdi), %rcx
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; SLOW-NEXT: movq %rax, 40(%rdi)
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; SLOW-NEXT: movq %rcx, 48(%rdi)
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; SLOW-NEXT: retq
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%idx0 = getelementptr i64, i64* %ptr, i64 0
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%idx1 = getelementptr i64, i64* %ptr, i64 1
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%ld0 = load i64, i64* %idx0, align 4
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%ld1 = load i64, i64* %idx1, align 4
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%idx4 = getelementptr i64, i64* %ptr, i64 5
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%idx5 = getelementptr i64, i64* %ptr, i64 6
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store i64 %ld0, i64* %idx4, align 4
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store i64 %ld1, i64* %idx5, align 4
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ret void
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}
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