| .. |
|
CallingConvLower.cpp
|
Add "inreg" field to CallSDNode (doesn't increase
|
2008-09-26 19:31:26 +00:00 |
|
CMakeLists.txt
|
Experimental post-pass scheduling support. Post-pass scheduling
|
2008-11-19 23:18:57 +00:00 |
|
DAGCombiner.cpp
|
Propagate debug location info for the token factor.
|
2009-01-30 01:13:16 +00:00 |
|
FastISel.cpp
|
Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.
|
2009-01-22 09:10:11 +00:00 |
|
LegalizeDAG.cpp
|
Explicitly add PseudoSourceValue information when lowering
|
2009-01-29 21:02:43 +00:00 |
|
LegalizeFloatTypes.cpp
|
Cleanup whitespace and comments, and tweak some
|
2009-01-21 09:00:29 +00:00 |
|
LegalizeIntegerTypes.cpp
|
Fixed extract element when the result needs to be promoted and the input widened.
|
2009-01-28 18:53:39 +00:00 |
|
LegalizeTypes.cpp
|
Fix PR3393, which amounts to a bug in the expensive
|
2009-01-26 21:54:18 +00:00 |
|
LegalizeTypes.h
|
Fix PR3393, which amounts to a bug in the expensive
|
2009-01-26 21:54:18 +00:00 |
|
LegalizeTypesGeneric.cpp
|
Preserve SourceValue information when lowering produces multiple loads from
|
2008-12-16 18:25:36 +00:00 |
|
LegalizeVectorTypes.cpp
|
Use ValueType::bitsLT to simplify some code.
|
2009-01-28 03:10:52 +00:00 |
|
Makefile
|
Removed trailing whitespace from Makefiles.
|
2009-01-09 16:44:42 +00:00 |
|
ScheduleDAGFast.cpp
|
Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
|
2009-01-15 19:20:50 +00:00 |
|
ScheduleDAGList.cpp
|
Initial hazard recognizer support in post-pass scheduling. This includes
|
2009-01-16 01:33:36 +00:00 |
|
ScheduleDAGRRList.cpp
|
Make a few things const, fix some comments, and simplify
|
2009-01-29 19:49:27 +00:00 |
|
ScheduleDAGSDNodes.cpp
|
CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions.
|
2009-01-16 20:57:18 +00:00 |
|
ScheduleDAGSDNodesEmit.cpp
|
Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.
|
2009-01-22 09:10:11 +00:00 |
|
SelectionDAG.cpp
|
In the case of an extractelement on an insertelement value,
|
2009-01-29 16:10:46 +00:00 |
|
SelectionDAGBuild.cpp
|
Propagate debug info when building SelectionDAG.
|
2009-01-30 01:34:22 +00:00 |
|
SelectionDAGBuild.h
|
Initial checkin of APInt'ififcation of switch lowering
|
2008-12-23 22:25:27 +00:00 |
|
SelectionDAGISel.cpp
|
Rename getAnalysisToUpdate to getAnalysisIfAvailable.
|
2009-01-28 13:14:17 +00:00 |
|
SelectionDAGPrinter.cpp
|
Use DebugInfo interface to lower dbg_* intrinsics.
|
2009-01-13 00:35:13 +00:00 |
|
TargetLowering.cpp
|
Fix two typos that Duncan spotted in a comment.
|
2009-01-29 16:18:12 +00:00 |
