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f387fa649a
Summary: Also minor cleanups: 1. Avoided multiple calls to Fixup.getKind() 2. Avoided multiple calls to getFixupKindInfo() 3. Removed a redundant return. Reviewers: asb, apazos Reviewed By: asb Subscribers: rbar, johnrusso, llvm-commits Differential Revision: https://reviews.llvm.org/D39881 llvm-svn: 317908
96 lines
3.3 KiB
C++
96 lines
3.3 KiB
C++
//===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the RISCV implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVRegisterInfo.h"
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#include "RISCV.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#define GET_REGINFO_TARGET_DESC
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#include "RISCVGenRegisterInfo.inc"
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using namespace llvm;
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RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
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: RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
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/*PC*/0, HwMode) {}
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const MCPhysReg *
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RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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return CSR_SaveList;
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}
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BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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// Use markSuperRegs to ensure any register aliases are also reserved
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markSuperRegs(Reserved, RISCV::X0); // zero
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markSuperRegs(Reserved, RISCV::X1); // ra
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markSuperRegs(Reserved, RISCV::X2); // sp
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markSuperRegs(Reserved, RISCV::X3); // gp
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markSuperRegs(Reserved, RISCV::X4); // tp
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markSuperRegs(Reserved, RISCV::X8); // fp
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assert(checkAllSuperRegsMarked(Reserved));
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return Reserved;
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}
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const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
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return CSR_NoRegs_RegMask;
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}
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void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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// TODO: this implementation is a temporary placeholder which does just
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// enough to allow other aspects of code generation to be tested
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assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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DebugLoc DL = MI.getDebugLoc();
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unsigned FrameReg = getFrameRegister(MF);
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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int Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg);
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Offset += MI.getOperand(FIOperandNum + 1).getImm();
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assert(TFI->hasFP(MF) && "eliminateFrameIndex currently requires hasFP");
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// Offsets must be directly encoded in a 12-bit immediate field
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if (!isInt<12>(Offset)) {
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report_fatal_error(
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"Frame offsets outside of the signed 12-bit range not supported");
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}
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MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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}
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unsigned RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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return RISCV::X8;
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}
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const uint32_t *
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RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & /*MF*/,
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CallingConv::ID /*CC*/) const {
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return CSR_RegMask;
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}
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