| .. |
|
AsmParser
|
[RISCV] MC layer support for the standard RV64I instructions
|
2017-12-07 10:53:48 +00:00 |
|
Disassembler
|
[RISCV] MC layer support for the standard RV32D instruction set extension
|
2017-12-07 10:46:23 +00:00 |
|
InstPrinter
|
[RISCV] MC layer support for the standard RV32F instruction set extension
|
2017-12-07 10:26:05 +00:00 |
|
MCTargetDesc
|
[RISCV] MC layer support for the standard RV32F instruction set extension
|
2017-12-07 10:26:05 +00:00 |
|
TargetInfo
|
Fix RISCV build after r318352
|
2017-11-16 18:39:31 +00:00 |
|
CMakeLists.txt
|
[RISCV] Initial codegen support for ALU operations
|
2017-10-19 21:37:38 +00:00 |
|
LLVMBuild.txt
|
[RISCV] Initial codegen support for ALU operations
|
2017-10-19 21:37:38 +00:00 |
|
RISCV.h
|
[RISCV] Codegen support for memory operations on global addresses
|
2017-11-08 13:24:21 +00:00 |
|
RISCV.td
|
[RISCV] MC layer support for the standard RV64I instructions
|
2017-12-07 10:53:48 +00:00 |
|
RISCVAsmPrinter.cpp
|
[RISCV] Codegen support for memory operations on global addresses
|
2017-11-08 13:24:21 +00:00 |
|
RISCVCallingConv.td
|
[RISCV] Codegen for conditional branches
|
2017-11-08 13:31:40 +00:00 |
|
RISCVFrameLowering.cpp
|
[RISCV] Initial codegen support for ALU operations
|
2017-10-19 21:37:38 +00:00 |
|
RISCVFrameLowering.h
|
[RISCV] Initial support for function calls
|
2017-11-08 13:41:21 +00:00 |
|
RISCVInstrFormats.td
|
[RISCV] MC layer support for the standard RV64I instructions
|
2017-12-07 10:53:48 +00:00 |
|
RISCVInstrInfo.cpp
|
[RISCV] Initial support for function calls
|
2017-11-08 13:41:21 +00:00 |
|
RISCVInstrInfo.h
|
[RISCV] Codegen for conditional branches
|
2017-11-08 13:31:40 +00:00 |
|
RISCVInstrInfo.td
|
[RISCV] MC layer support for the standard RV64I instructions
|
2017-12-07 10:53:48 +00:00 |
|
RISCVInstrInfoA.td
|
[RISCV] MC layer support for the standard RV32A instruction set extension
|
2017-11-09 15:00:03 +00:00 |
|
RISCVInstrInfoD.td
|
[RISCV] MC layer support for the standard RV32D instruction set extension
|
2017-12-07 10:46:23 +00:00 |
|
RISCVInstrInfoF.td
|
[RISCV] MC layer support for the standard RV32F instruction set extension
|
2017-12-07 10:26:05 +00:00 |
|
RISCVInstrInfoM.td
|
[RISCV] MC layer support for the standard RV64M instruction set extension
|
2017-12-07 10:56:07 +00:00 |
|
RISCVISelDAGToDAG.cpp
|
[RISCV][NFC] Clean up RISCVDAGToDAGISel::Select
|
2017-11-21 12:00:19 +00:00 |
|
RISCVISelLowering.cpp
|
[RISCV] Support and tests for a variety of additional LLVM IR constructs
|
2017-11-21 08:11:03 +00:00 |
|
RISCVISelLowering.h
|
[RISCV] Support and tests for a variety of additional LLVM IR constructs
|
2017-11-21 08:11:03 +00:00 |
|
RISCVMCInstLower.cpp
|
[RISCV] Support and tests for a variety of additional LLVM IR constructs
|
2017-11-21 08:11:03 +00:00 |
|
RISCVRegisterInfo.cpp
|
[RISCV] Silence an unused variable warning in release builds [NFC]
|
2017-11-10 19:09:28 +00:00 |
|
RISCVRegisterInfo.h
|
Fix a bunch more layering of CodeGen headers that are in Target
|
2017-11-17 01:07:10 +00:00 |
|
RISCVRegisterInfo.td
|
[RISCV] MC layer support for the standard RV32D instruction set extension
|
2017-12-07 10:46:23 +00:00 |
|
RISCVSubtarget.cpp
|
[RISCV] Initial codegen support for ALU operations
|
2017-10-19 21:37:38 +00:00 |
|
RISCVSubtarget.h
|
[RISCV] MC layer support for the standard RV32D instruction set extension
|
2017-12-07 10:46:23 +00:00 |
|
RISCVTargetMachine.cpp
|
[RISCV] Fix 64-bit data layout mismatch between backend and target description
|
2017-11-16 20:30:49 +00:00 |
|
RISCVTargetMachine.h
|
[RISCV] Initial codegen support for ALU operations
|
2017-10-19 21:37:38 +00:00 |
