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104 lines
3.7 KiB
LLVM
104 lines
3.7 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s
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; Test these 5 bitreverse store intrinsics:
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; Q6_bitrev_store_update_D(inputLR, pDelay, nConvLength);
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; Q6_bitrev_store_update_W(inputLR, pDelay, nConvLength);
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; Q6_bitrev_store_update_HL(inputLR, pDelay, nConvLength);
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; Q6_bitrev_store_update_HH(inputLR, pDelay, nConvLength);
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; Q6_bitrev_store_update_B(inputLR, pDelay, nConvLength);
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; producing these instructions:
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; memd(r0++m0:brev) = r1:0
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; memw(r0++m0:brev) = r0
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; memh(r0++m0:brev) = r3
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; memh(r0++m0:brev) = r3.h
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; memb(r0++m0:brev) = r3
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; ModuleID = 'brev_st.i'
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target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
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target triple = "hexagon"
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define i64 @foo(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
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entry:
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%conv = zext i16 %filtMemLen to i32
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%shr2 = lshr i32 %conv, 1
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%idxprom = sext i16 %filtMemIndex to i32
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%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
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%0 = bitcast i16* %arrayidx to i8*
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%sub = sub i32 13, %shr2
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%shl = shl i32 1, %sub
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; CHECK: memd(r{{[0-9]*}}++m{{[0-1]}}:brev)
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%1 = tail call i8* @llvm.hexagon.S2.storerd.pbr(i8* %0, i64 undef, i32 %shl)
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ret i64 0
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}
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declare i8* @llvm.hexagon.S2.storerd.pbr(i8*, i64, i32) nounwind
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define i32 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
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entry:
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%conv = zext i16 %filtMemLen to i32
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%shr1 = lshr i32 %conv, 1
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%idxprom = sext i16 %filtMemIndex to i32
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%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
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%0 = bitcast i16* %arrayidx to i8*
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%sub = sub i32 14, %shr1
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%shl = shl i32 1, %sub
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; CHECK: memw(r{{[0-9]*}}++m{{[0-1]}}:brev)
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%1 = tail call i8* @llvm.hexagon.S2.storeri.pbr(i8* %0, i32 undef, i32 %shl)
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ret i32 0
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}
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declare i8* @llvm.hexagon.S2.storeri.pbr(i8*, i32, i32) nounwind
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define signext i16 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
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entry:
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%conv = zext i16 %filtMemLen to i32
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%shr2 = lshr i32 %conv, 1
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%idxprom = sext i16 %filtMemIndex to i32
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%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
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%0 = bitcast i16* %arrayidx to i8*
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%sub = sub i32 15, %shr2
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%shl = shl i32 1, %sub
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; CHECK: memh(r{{[0-9]*}}++m{{[0-1]}}:brev)
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%1 = tail call i8* @llvm.hexagon.S2.storerh.pbr(i8* %0, i32 0, i32 %shl)
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ret i16 0
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}
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declare i8* @llvm.hexagon.S2.storerh.pbr(i8*, i32, i32) nounwind
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define signext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
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entry:
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%conv = zext i16 %filtMemLen to i32
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%shr2 = lshr i32 %conv, 1
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%idxprom = sext i16 %filtMemIndex to i32
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%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
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%0 = bitcast i16* %arrayidx to i8*
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%sub = sub i32 15, %shr2
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%shl = shl i32 1, %sub
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; CHECK: memh(r{{[0-9]*}}++m{{[0-1]}}:brev) = r{{[0-9]*}}.h
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%1 = tail call i8* @llvm.hexagon.S2.storerf.pbr(i8* %0, i32 0, i32 %shl)
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ret i16 0
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}
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declare i8* @llvm.hexagon.S2.storerf.pbr(i8*, i32, i32) nounwind
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define zeroext i8 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind {
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entry:
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%conv = zext i16 %filtMemLen to i32
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%shr2 = lshr i32 %conv, 1
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%idxprom = sext i16 %filtMemIndex to i32
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%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
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%0 = bitcast i16* %arrayidx to i8*
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%sub = sub nsw i32 16, %shr2
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; CHECK: memb(r{{[0-9]*}}++m{{[0-1]}}:brev)
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%shl = shl i32 1, %sub
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%1 = tail call i8* @llvm.hexagon.S2.storerb.pbr(i8* %0, i32 0, i32 %shl)
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ret i8 0
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}
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declare i8* @llvm.hexagon.S2.storerb.pbr(i8*, i32, i32) nounwind
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!0 = !{!"omnipotent char", !1}
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!1 = !{!"Simple C/C++ TBAA"}
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!2 = !{!"int", !0}
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!3 = !{!"short", !0}
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