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be591983cd
The 2nd loop calculates spill costs but reports free registers as cost 0 anyway, so there is little benefit from having a separate early loop. Surprisingly this is not NFC, as many register are marked regDisabled so the first loop often picks up later registers unnecessarily instead of the first one available in the allocation order... Patch by Matthias Braun llvm-svn: 356499
132 lines
2.6 KiB
LLVM
132 lines
2.6 KiB
LLVM
; RUN: llc -O0 -fast-isel -verify-machineinstrs -mtriple=arm64-eabi < %s | FileCheck --enable-var-scope %s
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; Test fptosi
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define i32 @fptosi_wh(half %a) nounwind ssp {
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entry:
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; CHECK-LABEL: fptosi_wh
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; CHECK: fcvt s1, h0
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; CHECK: fcvtzs [[REG:w[0-9]+]], s1
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; CHECK: mov w0, [[REG]]
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%conv = fptosi half %a to i32
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ret i32 %conv
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}
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; Test fptoui
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define i32 @fptoui_swh(half %a) nounwind ssp {
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entry:
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; CHECK-LABEL: fptoui_swh
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; CHECK: fcvt s1, h0
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; CHECK: fcvtzu [[REG:w[0-9]+]], s1
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; CHECK: mov w0, [[REG]]
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%conv = fptoui half %a to i32
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ret i32 %conv
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}
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; Test sitofp
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define half @sitofp_hw_i1(i1 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: sitofp_hw_i1
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; CHECK: sbfx w8, w0, #0, #1
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; CHECK: scvtf s0, w8
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; CHECK: fcvt h0, s0
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%conv = sitofp i1 %a to half
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ret half %conv
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}
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; Test sitofp
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define half @sitofp_hw_i8(i8 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: sitofp_hw_i8
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; CHECK: sxtb w8, w0
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; CHECK: scvtf s0, w8
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; CHECK: fcvt h0, s0
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%conv = sitofp i8 %a to half
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ret half %conv
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}
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; Test sitofp
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define half @sitofp_hw_i16(i16 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: sitofp_hw_i16
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; CHECK: sxth w8, w0
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; CHECK: scvtf s0, w8
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; CHECK: fcvt h0, s0
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%conv = sitofp i16 %a to half
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ret half %conv
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}
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; Test sitofp
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define half @sitofp_hw_i32(i32 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: sitofp_hw_i32
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; CHECK: scvtf s0, w0
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; CHECK: fcvt h0, s0
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%conv = sitofp i32 %a to half
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ret half %conv
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}
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; Test sitofp
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define half @sitofp_hx(i64 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: sitofp_hx
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; CHECK: scvtf s0, x0
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; CHECK: fcvt h0, s0
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%conv = sitofp i64 %a to half
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ret half %conv
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}
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; Test uitofp
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define half @uitofp_hw_i1(i1 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: uitofp_hw_i1
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; CHECK: and w8, w0, #0x1
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; CHECK: ucvtf s0, w8
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; CHECK: fcvt h0, s0
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%conv = uitofp i1 %a to half
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ret half %conv
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}
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; Test uitofp
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define half @uitofp_hw_i8(i8 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: uitofp_hw_i8
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; CHECK: and w8, w0, #0xff
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; CHECK: ucvtf s0, w8
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; CHECK: fcvt h0, s0
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%conv = uitofp i8 %a to half
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ret half %conv
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}
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; Test uitofp
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define half @uitofp_hw_i16(i16 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: uitofp_hw_i16
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; CHECK: and w8, w0, #0xffff
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; CHECK: ucvtf s0, w8
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; CHECK: fcvt h0, s0
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%conv = uitofp i16 %a to half
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ret half %conv
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}
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; Test uitofp
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define half @uitofp_hw_i32(i32 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: uitofp_hw_i32
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; CHECK: ucvtf s0, w0
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; CHECK: fcvt h0, s0
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%conv = uitofp i32 %a to half
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ret half %conv
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}
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; Test uitofp
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define half @uitofp_hx(i64 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: uitofp_hx
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; CHECK: ucvtf s0, x0
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; CHECK: fcvt h0, s0
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%conv = uitofp i64 %a to half
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ret half %conv
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}
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