Jessica Paquette ab6716fff2 [AArch64][GlobalISel] Don't write to WZR in non-flag-setting G_BRCOND case ... We are avoiding writing to WZR just about everywhere else. Also update the code to use MachineIRBuilder for the sake of consistency. We also didn't have a GlobalISel testcase for this path, so add a simple one now. Differential Revision: https://reviews.llvm.org/D90626		2020-12-01 16:45:37 -08:00
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AArch64CallLowering.cpp	AArch64/GlobalISel: Narrow stack passed argument access size	2020-09-25 13:35:17 -04:00
AArch64CallLowering.h	[SVE][CodeGen] Fix bug when falling back to DAG ISel	2020-07-07 09:23:04 +01:00
AArch64GlobalISelUtils.h	[AArch64][GlobalISel] Move imm adjustment for G_ICMP to post-legalizer lowering	2020-10-22 15:27:36 -07:00
AArch64InstructionSelector.cpp	[AArch64][GlobalISel] Don't write to WZR in non-flag-setting G_BRCOND case	2020-12-01 16:45:37 -08:00
AArch64LegalizerInfo.cpp	[AArch64][GlobalISel] Fix crash during legalization of a vector G_SELECT with scalar mask.	2020-11-30 16:37:49 -08:00
AArch64LegalizerInfo.h	[AArch64][GlobalISel] Use custom legalization for G_TRUNC for v8i8 vectors.	2020-10-01 13:22:00 -07:00
AArch64PostLegalizerCombiner.cpp	[AArch64][GlobalISel] Port some AArch64 target specific MUL combines from SDAG.	2020-11-10 22:21:13 -08:00
AArch64PostLegalizerLowering.cpp	[GlobalISel] Add matchers for specific constants and a matcher for negations	2020-11-13 09:24:54 -08:00
AArch64PostSelectOptimize.cpp	[AArch64][GlobalISel] Introduce a new post-isel optimization pass.	2020-10-23 10:18:36 -07:00
AArch64PreLegalizerCombiner.cpp	[AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0	2020-10-22 14:43:25 -07:00
AArch64RegisterBankInfo.cpp	[AArch64][GlobalISel] Regbankselect reductions to use FPR bank for scalars.	2020-10-16 10:42:15 -07:00
AArch64RegisterBankInfo.h	[AArch64][GlobalISel] Infer whether G_PHI is going to be a FPR in regbankselect	2020-09-28 10:37:09 -07:00