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llvm-mirror/lib/Target/AArch64
Kerry McLaughlin da93da7c53 [SVE][CodeGen] Call refineIndexType & refineUniformBase from visitMGATHER
The refineIndexType & refineUniformBase functions added by D90942 can also be used to
improve CodeGen of masked gathers.

These changes were split out from D91092

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D92319
2020-12-07 13:20:19 +00:00
..
AsmParser llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
Disassembler llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
GISel [AArch64][GlobalISel] Don't write to WZR in non-flag-setting G_BRCOND case 2020-12-01 16:45:37 -08:00
MCTargetDesc [Triple][MachO] Define "arm64e", an AArch64 subarch for Pointer Auth. 2020-12-03 07:53:59 -08:00
TargetInfo llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
Utils llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
AArch64.h [AArch64][GlobalISel] Introduce a new post-isel optimization pass. 2020-10-23 10:18:36 -07:00
AArch64.td [AArch64] Enable Cortex-A55 schedmodel 2020-11-30 19:28:34 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp [llvm][clang][mlir] Add checks for the return values from Target::createXXX to prevent protential null deref 2020-11-21 21:04:12 -08:00
AArch64BranchTargets.cpp
AArch64CallingConvention.cpp [SVE] Deal with SVE tuple call arguments correctly when running out of registers 2020-11-12 08:41:50 +00:00
AArch64CallingConvention.h
AArch64CallingConvention.td
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64Combine.td [AArch64][GlobalISel] Port some AArch64 target specific MUL combines from SDAG. 2020-11-10 22:21:13 -08:00
AArch64CompressJumpTables.cpp
AArch64CondBrTuning.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandImm.cpp
AArch64ExpandImm.h
AArch64ExpandPseudoInsts.cpp
AArch64FalkorHWPFFix.cpp
AArch64FastISel.cpp
AArch64FrameLowering.cpp Fix speling in comments. NFC. 2020-11-23 14:43:24 +00:00
AArch64FrameLowering.h [SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference. 2020-11-05 11:02:18 +00:00
AArch64GenRegisterBankInfo.def
AArch64InstrAtomics.td
AArch64InstrFormats.td
AArch64InstrGISel.td [AArch64][GlobalISel] Add AArch64::G_DUPLANE[X] opcodes for lane duplicates. 2020-11-05 11:18:11 -08:00
AArch64InstrInfo.cpp [NFCI] Replace AArch64StackOffset by StackOffset. 2020-11-04 08:49:00 +00:00
AArch64InstrInfo.h [NFCI] Replace AArch64StackOffset by StackOffset. 2020-11-04 08:49:00 +00:00
AArch64InstrInfo.td [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma and fmad nodes in tablegen. Remove explicit commuted patterns from targets. 2020-11-23 10:09:20 -08:00
AArch64ISelDAGToDAG.cpp [AArch64][SVE] Fix umin/umax lowering to handle out of range imm. 2020-10-23 09:42:56 -07:00
AArch64ISelLowering.cpp [SVE][CodeGen] Call refineIndexType & refineUniformBase from visitMGATHER 2020-12-07 13:20:19 +00:00
AArch64ISelLowering.h [SVE][CodeGen] Lower scalable masked gathers 2020-12-07 12:20:41 +00:00
AArch64LoadStoreOptimizer.cpp
AArch64MachineFunctionInfo.cpp
AArch64MachineFunctionInfo.h [MTE] Pin the tagged base pointer to one of the stack slots. 2020-10-15 12:50:16 -07:00
AArch64MacroFusion.cpp
AArch64MacroFusion.h
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PfmCounters.td
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp [SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference. 2020-11-05 11:02:18 +00:00
AArch64RegisterInfo.h
AArch64RegisterInfo.td
AArch64SchedA53.td
AArch64SchedA55.td [AArch64] Enable Cortex-A55 schedmodel 2020-11-30 19:28:34 +00:00
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64SchedExynosM3.td
AArch64SchedExynosM4.td
AArch64SchedExynosM5.td
AArch64SchedFalkor.td
AArch64SchedFalkorDetails.td
AArch64SchedKryo.td
AArch64SchedKryoDetails.td
AArch64SchedPredExynos.td
AArch64SchedPredicates.td
AArch64SchedThunderX2T99.td
AArch64SchedThunderX3T110.td
AArch64SchedThunderX.td
AArch64SchedTSV110.td [AArch64] Add pipeline model for HiSilicon's TSV110 2020-11-07 01:23:00 +03:00
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64SIMDInstrOpt.cpp
AArch64SLSHardening.cpp
AArch64SpeculationHardening.cpp
AArch64StackTagging.cpp Use cast<> instead of dyn_cast<> as we dereference the pointer immediately. NFCI. 2020-10-30 14:33:20 +00:00
AArch64StackTaggingPreRA.cpp [MTE] Pin the tagged base pointer to one of the stack slots. 2020-10-15 12:50:16 -07:00
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp [ARM][AArch64] Adding Neoverse N2 CPU support 2020-11-25 11:42:54 +00:00
AArch64Subtarget.h [ARM][AArch64] Adding Neoverse N2 CPU support 2020-11-25 11:42:54 +00:00
AArch64SVEInstrInfo.td [SVE][CodeGen] Lower scalable masked scatters 2020-11-11 11:50:22 +00:00
AArch64SystemOperands.td [AArch64] Enable RAS 1.1 system registers in all AArch64 2020-11-10 12:13:33 +00:00
AArch64TargetMachine.cpp [Triple][MachO] Define "arm64e", an AArch64 subarch for Pointer Auth. 2020-12-03 07:53:59 -08:00
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp [AArch64][CostModel] Fix cost for mul <2 x i64> 2020-11-30 11:36:55 +00:00
AArch64TargetTransformInfo.h [AArch64]Add memory op cost model for SVE 2020-11-11 12:49:19 +00:00
CMakeLists.txt llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
SVEInstrFormats.td [AArch64][SVE] Fix umin/umax lowering to handle out of range imm. 2020-10-23 09:42:56 -07:00
SVEIntrinsicOpts.cpp