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https://github.com/RPCS3/llvm-mirror.git
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495c7b3f90
The def instruction for the vreg may not match, because it may be folding through a reg_sequence. The assert was overly conservative and not necessary. It's not actually important if DefMI really defined the register, because the fold that will be done cares about the def of the value that will be folded. For some reason copies aren't making it through the reg_sequence, although they should. llvm-svn: 363876
312 lines
16 KiB
LLVM
312 lines
16 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SICI,SI %s
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; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefixes=GCN,SICI %s
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; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VIGFX9 %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,VIGFX9 %s
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; GCN-LABEL: {{^}}load_i32:
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; GCN-DAG: s_mov_b32 s3, 0
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; GCN-DAG: s_mov_b32 s2, s1
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; GCN-DAG: s_mov_b32 s1, s3
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; SICI-DAG: s_load_dword s{{[0-9]}}, s[0:1], 0x0
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; SICI-DAG: s_load_dword s{{[0-9]}}, s[2:3], 0x2
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; VIGFX9-DAG: s_load_dword s{{[0-9]}}, s[0:1], 0x0
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; VIGFX9-DAG: s_load_dword s{{[0-9]}}, s[2:3], 0x8
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define amdgpu_vs float @load_i32(i32 addrspace(6)* inreg %p0, i32 addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr inbounds i32, i32 addrspace(6)* %p1, i32 2
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%r0 = load i32, i32 addrspace(6)* %p0
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%r1 = load i32, i32 addrspace(6)* %gep1
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%r = add i32 %r0, %r1
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%r2 = bitcast i32 %r to float
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ret float %r2
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}
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; GCN-LABEL: {{^}}load_v2i32:
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; GCN-DAG: s_mov_b32 s3, 0
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; GCN-DAG: s_mov_b32 s2, s1
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; GCN-DAG: s_mov_b32 s1, s3
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; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
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; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x4
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; VIGFX9-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x10
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define amdgpu_vs <2 x float> @load_v2i32(<2 x i32> addrspace(6)* inreg %p0, <2 x i32> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(6)* %p1, i32 2
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%r0 = load <2 x i32>, <2 x i32> addrspace(6)* %p0
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%r1 = load <2 x i32>, <2 x i32> addrspace(6)* %gep1
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%r = add <2 x i32> %r0, %r1
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%r2 = bitcast <2 x i32> %r to <2 x float>
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ret <2 x float> %r2
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}
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; GCN-LABEL: {{^}}load_v4i32:
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; GCN-DAG: s_mov_b32 s3, 0
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; GCN-DAG: s_mov_b32 s2, s1
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; GCN-DAG: s_mov_b32 s1, s3
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; SICI-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
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; SICI-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x8
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; VIGFX9-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x20
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define amdgpu_vs <4 x float> @load_v4i32(<4 x i32> addrspace(6)* inreg %p0, <4 x i32> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(6)* %p1, i32 2
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%r0 = load <4 x i32>, <4 x i32> addrspace(6)* %p0
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%r1 = load <4 x i32>, <4 x i32> addrspace(6)* %gep1
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%r = add <4 x i32> %r0, %r1
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%r2 = bitcast <4 x i32> %r to <4 x float>
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ret <4 x float> %r2
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}
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; GCN-LABEL: {{^}}load_v8i32:
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; GCN-DAG: s_mov_b32 s3, 0
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; GCN-DAG: s_mov_b32 s2, s1
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; GCN-DAG: s_mov_b32 s1, s3
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; SICI-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
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; SICI-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x10
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; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x40
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define amdgpu_vs <8 x float> @load_v8i32(<8 x i32> addrspace(6)* inreg %p0, <8 x i32> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr inbounds <8 x i32>, <8 x i32> addrspace(6)* %p1, i32 2
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%r0 = load <8 x i32>, <8 x i32> addrspace(6)* %p0
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%r1 = load <8 x i32>, <8 x i32> addrspace(6)* %gep1
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%r = add <8 x i32> %r0, %r1
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%r2 = bitcast <8 x i32> %r to <8 x float>
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ret <8 x float> %r2
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}
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; GCN-LABEL: {{^}}load_v16i32:
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; GCN-DAG: s_mov_b32 s3, 0
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; GCN-DAG: s_mov_b32 s2, s1
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; GCN-DAG: s_mov_b32 s1, s3
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; SICI-DAG: s_load_dwordx16 s[{{.*}}], s[0:1], 0x0
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; SICI-DAG: s_load_dwordx16 s[{{.*}}], s[2:3], 0x20
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; VIGFX9-DAG: s_load_dwordx16 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx16 s[{{.*}}], s[2:3], 0x80
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define amdgpu_vs <16 x float> @load_v16i32(<16 x i32> addrspace(6)* inreg %p0, <16 x i32> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr inbounds <16 x i32>, <16 x i32> addrspace(6)* %p1, i32 2
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%r0 = load <16 x i32>, <16 x i32> addrspace(6)* %p0
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%r1 = load <16 x i32>, <16 x i32> addrspace(6)* %gep1
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%r = add <16 x i32> %r0, %r1
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%r2 = bitcast <16 x i32> %r to <16 x float>
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ret <16 x float> %r2
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}
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; GCN-LABEL: {{^}}load_float:
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; GCN-DAG: s_mov_b32 s3, 0
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; GCN-DAG: s_mov_b32 s2, s1
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; GCN-DAG: s_mov_b32 s1, s3
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; SICI-DAG: s_load_dword s{{[0-9]}}, s[0:1], 0x0
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; SICI-DAG: s_load_dword s{{[0-9]}}, s[2:3], 0x2
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; VIGFX9-DAG: s_load_dword s{{[0-9]}}, s[0:1], 0x0
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; VIGFX9-DAG: s_load_dword s{{[0-9]}}, s[2:3], 0x8
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define amdgpu_vs float @load_float(float addrspace(6)* inreg %p0, float addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr inbounds float, float addrspace(6)* %p1, i32 2
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%r0 = load float, float addrspace(6)* %p0
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%r1 = load float, float addrspace(6)* %gep1
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%r = fadd float %r0, %r1
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ret float %r
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}
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; GCN-LABEL: {{^}}load_v2float:
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; GCN-DAG: s_mov_b32 s3, 0
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; GCN-DAG: s_mov_b32 s2, s1
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; GCN-DAG: s_mov_b32 s1, s3
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; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
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; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x4
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; VIGFX9-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x10
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define amdgpu_vs <2 x float> @load_v2float(<2 x float> addrspace(6)* inreg %p0, <2 x float> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr inbounds <2 x float>, <2 x float> addrspace(6)* %p1, i32 2
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%r0 = load <2 x float>, <2 x float> addrspace(6)* %p0
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%r1 = load <2 x float>, <2 x float> addrspace(6)* %gep1
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%r = fadd <2 x float> %r0, %r1
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ret <2 x float> %r
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}
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; GCN-LABEL: {{^}}load_v4float:
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; GCN-DAG: s_mov_b32 s3, 0
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; GCN-DAG: s_mov_b32 s2, s1
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; GCN-DAG: s_mov_b32 s1, s3
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; SICI-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
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; SICI-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x8
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; VIGFX9-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x20
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define amdgpu_vs <4 x float> @load_v4float(<4 x float> addrspace(6)* inreg %p0, <4 x float> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr inbounds <4 x float>, <4 x float> addrspace(6)* %p1, i32 2
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%r0 = load <4 x float>, <4 x float> addrspace(6)* %p0
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%r1 = load <4 x float>, <4 x float> addrspace(6)* %gep1
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%r = fadd <4 x float> %r0, %r1
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ret <4 x float> %r
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}
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; GCN-LABEL: {{^}}load_v8float:
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; GCN-DAG: s_mov_b32 s3, 0
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; GCN-DAG: s_mov_b32 s2, s1
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; GCN-DAG: s_mov_b32 s1, s3
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; SICI-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
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; SICI-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x10
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; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x40
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define amdgpu_vs <8 x float> @load_v8float(<8 x float> addrspace(6)* inreg %p0, <8 x float> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr inbounds <8 x float>, <8 x float> addrspace(6)* %p1, i32 2
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%r0 = load <8 x float>, <8 x float> addrspace(6)* %p0
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%r1 = load <8 x float>, <8 x float> addrspace(6)* %gep1
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%r = fadd <8 x float> %r0, %r1
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ret <8 x float> %r
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}
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; GCN-LABEL: {{^}}load_v16float:
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; GCN-DAG: s_mov_b32 s3, 0
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; GCN-DAG: s_mov_b32 s2, s1
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; GCN-DAG: s_mov_b32 s1, s3
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; SICI-DAG: s_load_dwordx16 s[{{.*}}], s[0:1], 0x0
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; SICI-DAG: s_load_dwordx16 s[{{.*}}], s[2:3], 0x20
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; VIGFX9-DAG: s_load_dwordx16 s[{{.*}}], s[0:1], 0x0
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; VIGFX9-DAG: s_load_dwordx16 s[{{.*}}], s[2:3], 0x80
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define amdgpu_vs <16 x float> @load_v16float(<16 x float> addrspace(6)* inreg %p0, <16 x float> addrspace(6)* inreg %p1) #0 {
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%gep1 = getelementptr inbounds <16 x float>, <16 x float> addrspace(6)* %p1, i32 2
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%r0 = load <16 x float>, <16 x float> addrspace(6)* %p0
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%r1 = load <16 x float>, <16 x float> addrspace(6)* %gep1
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%r = fadd <16 x float> %r0, %r1
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ret <16 x float> %r
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}
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; GCN-LABEL: {{^}}load_i32_hi0:
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; GCN: s_mov_b32 s1, 0
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; GCN-NEXT: s_load_dword s0, s[0:1], 0x0
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define amdgpu_vs i32 @load_i32_hi0(i32 addrspace(6)* inreg %p) #1 {
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%r0 = load i32, i32 addrspace(6)* %p
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ret i32 %r0
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}
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; GCN-LABEL: {{^}}load_i32_hi1:
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; GCN: s_mov_b32 s1, 1
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; GCN-NEXT: s_load_dword s0, s[0:1], 0x0
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define amdgpu_vs i32 @load_i32_hi1(i32 addrspace(6)* inreg %p) #2 {
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%r0 = load i32, i32 addrspace(6)* %p
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ret i32 %r0
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}
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; GCN-LABEL: {{^}}load_i32_hiffff8000:
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; GCN: s_movk_i32 s1, 0x8000
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; GCN-NEXT: s_load_dword s0, s[0:1], 0x0
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define amdgpu_vs i32 @load_i32_hiffff8000(i32 addrspace(6)* inreg %p) #3 {
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%r0 = load i32, i32 addrspace(6)* %p
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ret i32 %r0
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}
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; GCN-LABEL: {{^}}load_i32_hifffffff0:
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; GCN: s_mov_b32 s1, -16
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; GCN-NEXT: s_load_dword s0, s[0:1], 0x0
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define amdgpu_vs i32 @load_i32_hifffffff0(i32 addrspace(6)* inreg %p) #4 {
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%r0 = load i32, i32 addrspace(6)* %p
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ret i32 %r0
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}
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; GCN-LABEL: {{^}}load_sampler
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; GCN: v_readfirstlane_b32
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; GCN-NEXT: v_readfirstlane_b32
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; SI: s_nop
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; GCN: s_load_dwordx8
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; GCN-NEXT: s_load_dwordx4
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; GCN: image_sample
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define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @load_sampler([0 x <4 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), [0 x <8 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), [0 x <4 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), [0 x <8 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #5 {
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main_body:
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%22 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %5) #8
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%23 = bitcast float %22 to i32
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%24 = shl i32 %23, 1
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%25 = getelementptr inbounds [0 x <8 x i32>], [0 x <8 x i32>] addrspace(6)* %1, i32 0, i32 %24, !amdgpu.uniform !0
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%26 = load <8 x i32>, <8 x i32> addrspace(6)* %25, align 32, !invariant.load !0
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%27 = shl i32 %23, 2
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%28 = or i32 %27, 3
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%29 = bitcast [0 x <8 x i32>] addrspace(6)* %1 to [0 x <4 x i32>] addrspace(6)*
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%30 = getelementptr inbounds [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %29, i32 0, i32 %28, !amdgpu.uniform !0
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%31 = load <4 x i32>, <4 x i32> addrspace(6)* %30, align 16, !invariant.load !0
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%32 = call nsz <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float 0.0, <8 x i32> %26, <4 x i32> %31, i1 0, i32 0, i32 0) #8
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%33 = extractelement <4 x float> %32, i32 0
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%34 = extractelement <4 x float> %32, i32 1
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%35 = extractelement <4 x float> %32, i32 2
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%36 = extractelement <4 x float> %32, i32 3
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%37 = bitcast float %4 to i32
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%38 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %37, 4
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%39 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %38, float %33, 5
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%40 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %39, float %34, 6
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%41 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %40, float %35, 7
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%42 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %41, float %36, 8
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%43 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %42, float %20, 19
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ret <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %43
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}
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; GCN-LABEL: {{^}}load_sampler_nouniform
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; GCN: v_readfirstlane_b32
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; GCN-NEXT: v_readfirstlane_b32
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; SI: s_nop
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; GCN: s_load_dwordx8
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; GCN-NEXT: s_load_dwordx4
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; GCN: image_sample
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define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @load_sampler_nouniform([0 x <4 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), [0 x <8 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), [0 x <4 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), [0 x <8 x i32>] addrspace(6)* inreg noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #5 {
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main_body:
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%22 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %5) #8
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%23 = bitcast float %22 to i32
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%24 = shl i32 %23, 1
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%25 = getelementptr inbounds [0 x <8 x i32>], [0 x <8 x i32>] addrspace(6)* %1, i32 0, i32 %24
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%26 = load <8 x i32>, <8 x i32> addrspace(6)* %25, align 32, !invariant.load !0
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%27 = shl i32 %23, 2
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%28 = or i32 %27, 3
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%29 = bitcast [0 x <8 x i32>] addrspace(6)* %1 to [0 x <4 x i32>] addrspace(6)*
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%30 = getelementptr inbounds [0 x <4 x i32>], [0 x <4 x i32>] addrspace(6)* %29, i32 0, i32 %28
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%31 = load <4 x i32>, <4 x i32> addrspace(6)* %30, align 16, !invariant.load !0
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%32 = call nsz <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float 0.0, <8 x i32> %26, <4 x i32> %31, i1 0, i32 0, i32 0) #8
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%33 = extractelement <4 x float> %32, i32 0
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%34 = extractelement <4 x float> %32, i32 1
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%35 = extractelement <4 x float> %32, i32 2
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%36 = extractelement <4 x float> %32, i32 3
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%37 = bitcast float %4 to i32
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%38 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %37, 4
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%39 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %38, float %33, 5
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%40 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %39, float %34, 6
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%41 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %40, float %35, 7
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%42 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %41, float %36, 8
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%43 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %42, float %20, 19
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ret <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %43
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}
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; GCN-LABEL: {{^}}load_addr_no_fold:
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; GCN-DAG: s_add_i32 s0, s0, 4
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; GCN-DAG: s_mov_b32 s1, 0
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; GCN: s_load_dword s{{[0-9]}}, s[0:1], 0x0
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define amdgpu_vs float @load_addr_no_fold(i32 addrspace(6)* inreg noalias %p0) #0 {
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%gep1 = getelementptr i32, i32 addrspace(6)* %p0, i32 1
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%r1 = load i32, i32 addrspace(6)* %gep1
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%r2 = bitcast i32 %r1 to float
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ret float %r2
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}
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; CHECK-LABEL: {{^}}vgpr_arg_src:
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; CHECK: v_readfirstlane_b32 s[[READLANE:[0-9]+]], v0
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; CHECK: s_mov_b32 s[[ZERO:[0-9]+]]
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; CHECK: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[READLANE]]:[[ZERO]]{{\]}}
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define amdgpu_vs float @vgpr_arg_src(<4 x i32> addrspace(6)* %arg) {
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main_body:
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%tmp9 = load <4 x i32>, <4 x i32> addrspace(6)* %arg
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|
%tmp10 = call nsz float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp9, i32 undef, i32 0, i32 0, i32 0) #1
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ret float %tmp10
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|
}
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|
; Function Attrs: nounwind readnone speculatable
|
|
declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #6
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|
|
; Function Attrs: nounwind readonly
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|
declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #7
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|
|
|
declare float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32>, i32, i32, i32, i32) #7
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|
|
!0 = !{}
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|
|
|
attributes #0 = { nounwind }
|
|
attributes #1 = { nounwind "amdgpu-32bit-address-high-bits"="0" }
|
|
attributes #2 = { nounwind "amdgpu-32bit-address-high-bits"="1" }
|
|
attributes #3 = { nounwind "amdgpu-32bit-address-high-bits"="0xffff8000" }
|
|
attributes #4 = { nounwind "amdgpu-32bit-address-high-bits"="0xfffffff0" }
|
|
attributes #5 = { "InitialPSInputAddr"="45175" }
|
|
attributes #6 = { nounwind readnone speculatable }
|
|
attributes #7 = { nounwind readonly }
|
|
attributes #8 = { nounwind readnone }
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