mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 20:51:52 +01:00
5bba32a441
This was broken if the original operand was killed. The kill flag would appear on both instructions, and fail the verifier. Keep the kill flag, but remove the operands from the old instruction. This has an added benefit of really reducing the use count for future folds. Ideally the pass would be structured more like what PeepholeOptimizer does to avoid this hack to avoid breaking instruction iterators. llvm-svn: 359891
649 lines
20 KiB
YAML
649 lines
20 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: shrink_scalar_imm_vgpr_v_add_i32_e64_no_carry_out_use
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_no_carry_out_use
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
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%0:sreg_32_xm0 = S_MOV_B32 12345
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
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S_ENDPGM 0, implicit %2
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...
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---
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name: shrink_vgpr_scalar_imm_v_add_i32_e64_no_carry_out_use
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_add_i32_e64_no_carry_out_use
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
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%0:vgpr_32 = IMPLICIT_DEF
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%1:sreg_32_xm0 = S_MOV_B32 12345
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%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
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S_ENDPGM 0, implicit %2
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...
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---
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name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
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%0:sreg_32_xm0 = S_MOV_B32 12345
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
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S_ENDPGM 0, implicit %2
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...
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---
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# This does not shrink because it would violate the constant bus
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# restriction. to have an SGPR input and an immediate, so a copy would
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# be required.
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name: shrink_vector_imm_sgpr_v_add_i32_e64_no_carry_out_use
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: shrink_vector_imm_sgpr_v_add_i32_e64_no_carry_out_use
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; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
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; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[DEF]], [[V_MOV_B32_e32_]], 0, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
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%0:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
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%1:sreg_32_xm0 = IMPLICIT_DEF
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%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
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S_ENDPGM 0, implicit %2
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...
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---
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name: shrink_sgpr_vector_imm_v_add_i32_e64_no_carry_out_use
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: shrink_sgpr_vector_imm_v_add_i32_e64_no_carry_out_use
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; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
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; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[V_MOV_B32_e32_]], [[DEF]], 0, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]]
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%0:sreg_32_xm0 = IMPLICIT_DEF
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%1:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
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%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
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S_ENDPGM 0, implicit %2
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...
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---
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name: shrink_scalar_imm_vgpr_v_add_i32_e64_live_vcc_use
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_live_vcc_use
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; GCN: $vcc = S_MOV_B64 -1
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit $vcc
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$vcc = S_MOV_B64 -1
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%0:sreg_32_xm0 = S_MOV_B32 12345
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
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S_ENDPGM 0, implicit %2, implicit $vcc
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...
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---
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name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_use
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_use
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: $vcc = S_MOV_B64 -1
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec
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; GCN: bb.1:
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; GCN: liveins: $vcc
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit $vcc
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bb.0:
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successors: %bb.1
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$vcc = S_MOV_B64 -1
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%0:sreg_32_xm0 = S_MOV_B32 12345
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
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bb.1:
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liveins: $vcc
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S_ENDPGM 0, implicit %2, implicit $vcc
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...
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---
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name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_lo_use
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_lo_use
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec
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; GCN: bb.1:
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; GCN: liveins: $vcc_lo
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit $vcc_lo
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bb.0:
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successors: %bb.1
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$vcc = S_MOV_B64 -1
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%0:sreg_32_xm0 = S_MOV_B32 12345
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
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bb.1:
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liveins: $vcc_lo
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S_ENDPGM 0, implicit %2, implicit $vcc_lo
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...
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---
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# This is not OK to clobber because vcc_lo has a livein use.
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name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: $vcc = S_MOV_B64 -1
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; GCN: bb.1:
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; GCN: liveins: $vcc
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit $vcc_lo
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bb.0:
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successors: %bb.1
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$vcc = S_MOV_B64 -1
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bb.1:
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liveins: $vcc
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%0:sreg_32_xm0 = S_MOV_B32 12345
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
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S_ENDPGM 0, implicit %2, implicit $vcc_lo
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...
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---
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name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc_hi
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc_hi
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: $vcc_hi = S_MOV_B32 -1
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; GCN: bb.1:
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; GCN: successors: %bb.2(0x80000000)
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; GCN: liveins: $vcc_hi
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec
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; GCN: bb.2:
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; GCN: liveins: $vcc_hi
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit $vcc_hi
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bb.0:
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successors: %bb.1
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$vcc_hi = S_MOV_B32 -1
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bb.1:
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liveins: $vcc_hi
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%0:sreg_32_xm0 = S_MOV_B32 12345
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
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bb.2:
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liveins: $vcc_hi
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S_ENDPGM 0, implicit %2, implicit $vcc_hi
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...
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---
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name: shrink_scalar_imm_vgpr_v_sub_i32_e64_no_carry_out_use
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_sub_i32_e64_no_carry_out_use
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[V_SUB_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_SUB_I32_e32_]]
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%0:sreg_32_xm0 = S_MOV_B32 12345
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32, %3:sreg_64 = V_SUB_I32_e64 %0, %1, 0, implicit $exec
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S_ENDPGM 0, implicit %2
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...
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---
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name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[V_SUBREV_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_SUBREV_I32_e32_]]
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%0:vgpr_32 = IMPLICIT_DEF
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%1:sreg_32_xm0 = S_MOV_B32 12345
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%2:vgpr_32, %3:sreg_64 = V_SUB_I32_e64 %0, %1, 0, implicit $exec
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S_ENDPGM 0, implicit %2
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...
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---
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name: shrink_scalar_imm_vgpr_v_subrev_i32_e64_no_carry_out_use
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_subrev_i32_e64_no_carry_out_use
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[V_SUBREV_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_SUBREV_I32_e32_]]
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%0:sreg_32_xm0 = S_MOV_B32 12345
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32, %3:sreg_64 = V_SUBREV_I32_e64 %0, %1, 0, implicit $exec
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S_ENDPGM 0, implicit %2
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...
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---
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name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[V_SUB_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_SUB_I32_e32_]]
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%0:vgpr_32 = IMPLICIT_DEF
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%1:sreg_32_xm0 = S_MOV_B32 12345
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%2:vgpr_32, %3:sreg_64 = V_SUBREV_I32_e64 %0, %1, 0, implicit $exec
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S_ENDPGM 0, implicit %2
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...
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---
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# We know this is OK because vcc isn't live out of the block.
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name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
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; GCN: bb.1:
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; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
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bb.0:
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successors: %bb.1
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S_NOP 0
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S_NOP 0
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S_NOP 0
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S_NOP 0
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S_NOP 0
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S_NOP 0
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S_NOP 0
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S_NOP 0
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|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
%0:sreg_32_xm0 = S_MOV_B32 12345
|
|
%1:vgpr_32 = IMPLICIT_DEF
|
|
%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
|
|
S_NOP 0
|
|
S_NOP 0
|
|
|
|
bb.1:
|
|
S_ENDPGM 0, implicit %2
|
|
|
|
...
|
|
|
|
---
|
|
|
|
# We know this is OK because vcc isn't live out of the block, even
|
|
# though it had a defined but unused. value
|
|
|
|
name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout_dead_vcc_def
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout_dead_vcc_def
|
|
; GCN: bb.0:
|
|
; GCN: successors: %bb.1(0x80000000)
|
|
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
|
|
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
|
|
; GCN: bb.1:
|
|
; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
|
|
bb.0:
|
|
successors: %bb.1
|
|
|
|
S_NOP 0, implicit-def $vcc
|
|
%0:sreg_32_xm0 = S_MOV_B32 12345
|
|
%1:vgpr_32 = IMPLICIT_DEF
|
|
%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
|
|
S_NOP 0
|
|
S_NOP 0
|
|
|
|
bb.1:
|
|
S_ENDPGM 0, implicit %2
|
|
|
|
...
|
|
---
|
|
|
|
# This requires searching through many DBG_VALUE instructions before the insert poitn, which
|
|
# should not count against the search limit.
|
|
|
|
name: vcc_liveness_dbg_value_search_before
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
; GCN-LABEL: name: vcc_liveness_dbg_value_search_before
|
|
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
|
|
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
|
|
; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
|
|
%0:sreg_32_xm0 = S_MOV_B32 12345
|
|
%1:vgpr_32 = IMPLICIT_DEF
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
|
|
S_ENDPGM 0, implicit %2
|
|
|
|
...
|
|
---
|
|
|
|
# This requires searching through many DBG_VALUE instructions after the insert point, which
|
|
# should not count against the search limit.
|
|
|
|
name: vcc_liveness_dbg_value_search_after
|
|
tracksRegLiveness: true
|
|
|
|
body: |
|
|
bb.0:
|
|
; GCN-LABEL: name: vcc_liveness_dbg_value_search_after
|
|
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
|
|
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: DBG_VALUE $noreg, 0
|
|
; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
|
|
%0:sreg_32_xm0 = S_MOV_B32 12345
|
|
%1:vgpr_32 = IMPLICIT_DEF
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
S_NOP 0
|
|
%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
DBG_VALUE $noreg, 0
|
|
$vcc = S_MOV_B64 0
|
|
S_ENDPGM 0, implicit %2
|
|
|
|
...
|
|
|
|
---
|
|
name: shrink_add_kill_flags_src0
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
; GCN-LABEL: name: shrink_add_kill_flags_src0
|
|
; GCN: liveins: $vgpr0
|
|
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
|
|
; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 killed [[V_MOV_B32_e32_]], [[COPY]], implicit-def $vcc, implicit $exec
|
|
; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
|
|
%0:vgpr_32 = COPY $vgpr0
|
|
%1:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
|
|
%2:vgpr_32, %3:sreg_64_xexec = V_ADD_I32_e64 killed %1, %0, 0, implicit $exec
|
|
S_ENDPGM 0, implicit %2
|
|
...
|
|
|
|
---
|
|
name: shrink_add_kill_flags_src1
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
; GCN-LABEL: name: shrink_add_kill_flags_src1
|
|
; GCN: liveins: $vgpr0
|
|
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
|
|
; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[V_MOV_B32_e32_]], killed [[COPY]], implicit-def $vcc, implicit $exec
|
|
; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]]
|
|
%0:vgpr_32 = COPY $vgpr0
|
|
%1:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
|
|
%2:vgpr_32, %3:sreg_64_xexec = V_ADD_I32_e64 %1, killed %0, 0, implicit $exec
|
|
S_ENDPGM 0, implicit %2
|
|
...
|
|
|
|
---
|
|
name: shrink_addc_kill_flags_src2
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0, $vcc
|
|
; GCN-LABEL: name: shrink_addc_kill_flags_src2
|
|
; GCN: liveins: $vgpr0, $vcc
|
|
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
|
|
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $vcc
|
|
; GCN: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADDC_U32_e64 [[V_MOV_B32_e32_]], [[COPY]], [[COPY1]], 0, implicit $exec
|
|
; GCN: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]]
|
|
%0:vgpr_32 = COPY $vgpr0
|
|
%1:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
|
|
%2:sreg_64_xexec = COPY $vcc
|
|
%3:vgpr_32, %4:sreg_64_xexec = V_ADDC_U32_e64 %1, %0, %2, 0, implicit $exec
|
|
S_ENDPGM 0, implicit %3
|
|
...
|