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c5d6744168
Support sub-register code-gen for XADD is like supporting any other Load and Store patterns. No new instruction is introduced. lock *(u32 *)(r1 + 0) += w2 has exactly the same underlying insn as: lock *(u32 *)(r1 + 0) += r2 BPF_W width modifier has guaranteed they behave the same at runtime. This patch merely teaches BPF back-end that BPF_W width modifier could work GPR32 register class and that's all needed for sub-register code-gen support for XADD. test/CodeGen/BPF/xadd.ll updated to include sub-register code-gen tests. A new testcase test/CodeGen/BPF/xadd_legal.ll is added to make sure the legal case could pass on all code-gen modes. It could also test dead Def check on GPR32. If there is no proper handling like what has been done inside BPFMIChecking.cpp:hasLivingDefs, then this testcase will fail. Acked-by: Yonghong Song <yhs@fb.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> llvm-svn: 355126
27 lines
1.0 KiB
LLVM
27 lines
1.0 KiB
LLVM
; RUN: llc -march=bpfel < %s 2>&1 | FileCheck --check-prefix=CHECK-64 %s
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; RUN: llc -march=bpfeb < %s 2>&1 | FileCheck --check-prefix=CHECK-64 %s
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; RUN: llc -march=bpfel -mattr=+alu32 < %s 2>&1 | FileCheck --check-prefix=CHECK-32 %s
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; RUN: llc -march=bpfeb -mattr=+alu32 < %s 2>&1 | FileCheck --check-prefix=CHECK-32 %s
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; This file is generated with the source command and source
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; $ clang -target bpf -O2 -S -emit-llvm t.c
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; $ cat t.c
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; int test(int *ptr, unsigned long long a) {
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; __sync_fetch_and_add(ptr, a);
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; return *ptr;
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; }
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;
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; NOTE: passing unsigned long long as the second operand of __sync_fetch_and_add
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; could effectively create sub-register reference coming from indexing a full
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; register which could then exerceise hasLivingDefs inside BPFMIChecker.cpp.
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define dso_local i32 @test(i32* nocapture %ptr, i64 %a) {
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entry:
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%conv = trunc i64 %a to i32
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%0 = atomicrmw add i32* %ptr, i32 %conv seq_cst
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; CHECK-64: lock *(u32 *)(r1 + 0) += r2
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; CHECK-32: lock *(u32 *)(r1 + 0) += w2
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%1 = load i32, i32* %ptr, align 4
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ret i32 %1
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}
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