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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 18:54:02 +01:00
llvm-mirror/test/CodeGen/MIR
Matt Arsenault cc12b285b6 CodeGen: Print/parse LLTs in MachineMemOperands
This will currently accept the old number of bytes syntax, and convert
it to a scalar. This should be removed in the near future (I think I
converted all of the tests already, but likely missed a few).

Not sure what the exact syntax and policy should be. We can continue
printing the number of bytes for non-generic instructions to avoid
test churn and only allow non-scalar types for generic instructions.

This will currently print the LLT in parentheses, but accept parsing
the existing integers and implicitly converting to scalar. The
parentheses are a bit ugly, but the parser logic seems unable to deal
without either parentheses or some keyword to indicate the start of a
type.
2021-06-30 16:54:13 -04:00
..
AArch64 CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
AMDGPU CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ARM CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
Generic [MIRParser] Add machine metadata. 2021-06-28 22:29:36 -04:00
Hexagon CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
Mips CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
NVPTX
PowerPC CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
WebAssembly
X86 CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.