1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00
llvm-mirror/test/CodeGen
2021-06-23 16:31:19 +03:00
..
AArch64 [AArch64] Add CodeGen tests for vector reduction intrinsics. NFC 2021-06-23 13:46:16 +01:00
AMDGPU [AMDGPU] Propagate LDS align into to instructions 2021-06-23 00:57:16 -07:00
ARC
ARM [NFC][ARM] Fix update_llc_test_checks for thumbv7-apple-ios, autogenerate switch-minsize.ll 2021-06-23 16:31:19 +03:00
AVR
BPF
Generic Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
Hexagon [NFC][AArch64][ARM][Thumb][Hexagon] Autogenerate some tests 2021-06-20 14:12:45 +03:00
Inputs
Lanai
M68k [M68k] Add testcases for shift and rotate instructions 2021-06-23 13:26:58 +08:00
Mips Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
MIR Implement DW_CFA_LLVM_* for Heterogeneous Debugging 2021-06-14 08:51:50 +05:30
MSP430
NVPTX Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
PowerPC [AIX][XCOFF] generate eh_info when vector registers are saved according to the traceback table. 2021-06-22 13:01:31 -04:00
RISCV [Verifier] Fail on overrunning and invalid indices for {insert,extract} vector intrinsics 2021-06-23 10:33:22 +00:00
SPARC [SPARC] Legalize truncation and extension between fp128 and half 2021-06-13 20:05:15 +02:00
SystemZ Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
Thumb [ARM] Make sure we don't transform unaligned store to stm on Thumb1. 2021-06-21 14:32:42 -07:00
Thumb2 [ARM] Transform a fixed-point to floating-point conversion into a VCVT_fix 2021-06-21 14:14:09 +01:00
VE
WebAssembly [WebAssembly] Rename event to tag 2021-06-17 20:34:19 -07:00
WinCFGuard
WinEH
X86 Improve the diagnostic of DiagnosticInfoResourceLimit (and warn-stack-size in particular) 2021-06-22 09:55:20 -07:00
XCore Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00