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145 lines
4.9 KiB
LLVM
145 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s --check-prefixes=CHECK,CHECK-NOARG
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; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ARG
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target triple = "aarch64-unknown-linux-gnu"
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define void @func_vscale_none(<16 x i32>* %a, <16 x i32>* %b) #0 {
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; CHECK-NOARG-LABEL: func_vscale_none:
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; CHECK-NOARG: // %bb.0:
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; CHECK-NOARG-NEXT: ldp q0, q1, [x0]
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; CHECK-NOARG-NEXT: ldp q2, q3, [x1]
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; CHECK-NOARG-NEXT: ldp q4, q5, [x0, #32]
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; CHECK-NOARG-NEXT: ldp q7, q6, [x1, #32]
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; CHECK-NOARG-NEXT: add v1.4s, v1.4s, v3.4s
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; CHECK-NOARG-NEXT: add v0.4s, v0.4s, v2.4s
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; CHECK-NOARG-NEXT: add v2.4s, v5.4s, v6.4s
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; CHECK-NOARG-NEXT: add v3.4s, v4.4s, v7.4s
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; CHECK-NOARG-NEXT: stp q3, q2, [x0, #32]
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; CHECK-NOARG-NEXT: stp q0, q1, [x0]
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; CHECK-NOARG-NEXT: ret
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;
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; CHECK-ARG-LABEL: func_vscale_none:
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; CHECK-ARG: // %bb.0:
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; CHECK-ARG-NEXT: ptrue p0.s, vl16
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; CHECK-ARG-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-ARG-NEXT: ld1w { z1.s }, p0/z, [x1]
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; CHECK-ARG-NEXT: add z0.s, p0/m, z0.s, z1.s
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; CHECK-ARG-NEXT: st1w { z0.s }, p0, [x0]
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; CHECK-ARG-NEXT: ret
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%op1 = load <16 x i32>, <16 x i32>* %a
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%op2 = load <16 x i32>, <16 x i32>* %b
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%res = add <16 x i32> %op1, %op2
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store <16 x i32> %res, <16 x i32>* %a
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ret void
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}
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attributes #0 = { "target-features"="+sve" }
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define void @func_vscale1_1(<16 x i32>* %a, <16 x i32>* %b) #1 {
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; CHECK-LABEL: func_vscale1_1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ldp q2, q3, [x1]
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; CHECK-NEXT: ldp q4, q5, [x0, #32]
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; CHECK-NEXT: ldp q7, q6, [x1, #32]
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; CHECK-NEXT: add v1.4s, v1.4s, v3.4s
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; CHECK-NEXT: add v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: add v2.4s, v5.4s, v6.4s
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; CHECK-NEXT: add v3.4s, v4.4s, v7.4s
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; CHECK-NEXT: stp q3, q2, [x0, #32]
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x i32>, <16 x i32>* %a
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%op2 = load <16 x i32>, <16 x i32>* %b
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%res = add <16 x i32> %op1, %op2
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store <16 x i32> %res, <16 x i32>* %a
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ret void
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}
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attributes #1 = { "target-features"="+sve" vscale_range(1,1) }
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define void @func_vscale2_2(<16 x i32>* %a, <16 x i32>* %b) #2 {
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; CHECK-LABEL: func_vscale2_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl8
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; CHECK-NEXT: add x8, x0, #32 // =32
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; CHECK-NEXT: add x9, x1, #32 // =32
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x8]
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; CHECK-NEXT: ld1w { z2.s }, p0/z, [x1]
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; CHECK-NEXT: ld1w { z3.s }, p0/z, [x9]
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; CHECK-NEXT: add z0.s, p0/m, z0.s, z2.s
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; CHECK-NEXT: add z1.s, p0/m, z1.s, z3.s
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; CHECK-NEXT: st1w { z0.s }, p0, [x0]
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; CHECK-NEXT: st1w { z1.s }, p0, [x8]
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; CHECK-NEXT: ret
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%op1 = load <16 x i32>, <16 x i32>* %a
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%op2 = load <16 x i32>, <16 x i32>* %b
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%res = add <16 x i32> %op1, %op2
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store <16 x i32> %res, <16 x i32>* %a
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ret void
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}
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attributes #2 = { "target-features"="+sve" vscale_range(2,2) }
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define void @func_vscale2_4(<16 x i32>* %a, <16 x i32>* %b) #3 {
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; CHECK-LABEL: func_vscale2_4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl8
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; CHECK-NEXT: add x8, x0, #32 // =32
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; CHECK-NEXT: add x9, x1, #32 // =32
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x8]
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; CHECK-NEXT: ld1w { z2.s }, p0/z, [x1]
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; CHECK-NEXT: ld1w { z3.s }, p0/z, [x9]
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; CHECK-NEXT: add z0.s, p0/m, z0.s, z2.s
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; CHECK-NEXT: add z1.s, p0/m, z1.s, z3.s
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; CHECK-NEXT: st1w { z0.s }, p0, [x0]
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; CHECK-NEXT: st1w { z1.s }, p0, [x8]
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; CHECK-NEXT: ret
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%op1 = load <16 x i32>, <16 x i32>* %a
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%op2 = load <16 x i32>, <16 x i32>* %b
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%res = add <16 x i32> %op1, %op2
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store <16 x i32> %res, <16 x i32>* %a
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ret void
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}
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attributes #3 = { "target-features"="+sve" vscale_range(2,4) }
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define void @func_vscale4_4(<16 x i32>* %a, <16 x i32>* %b) #4 {
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; CHECK-LABEL: func_vscale4_4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl16
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
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; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: st1w { z0.s }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x i32>, <16 x i32>* %a
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%op2 = load <16 x i32>, <16 x i32>* %b
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%res = add <16 x i32> %op1, %op2
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store <16 x i32> %res, <16 x i32>* %a
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ret void
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}
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attributes #4 = { "target-features"="+sve" vscale_range(4,4) }
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define void @func_vscale8_8(<16 x i32>* %a, <16 x i32>* %b) #5 {
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; CHECK-LABEL: func_vscale8_8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl16
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
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; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: st1w { z0.s }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x i32>, <16 x i32>* %a
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%op2 = load <16 x i32>, <16 x i32>* %b
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%res = add <16 x i32> %op1, %op2
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store <16 x i32> %res, <16 x i32>* %a
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ret void
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}
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attributes #5 = { "target-features"="+sve" vscale_range(8,8) }
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