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935e65cc31
Mark MULHS/MULHU nodes as legal for both scalable and fixed SVE types, and lower them to the appropriate SVE instructions. Additionally now that the MULH nodes are legal, integer divides can be expanded into a more performant code sequence. Differential Revision: https://reviews.llvm.org/D100487
133 lines
5.5 KiB
LLVM
133 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s
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;
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; SMULH
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;
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define <vscale x 16 x i8> @smulh_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: smulh_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smulh z0.b, z0.b, z1.b
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; CHECK-NEXT: ret
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%insert = insertelement <vscale x 16 x i16> undef, i16 8, i64 0
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%splat = shufflevector <vscale x 16 x i16> %insert, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
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%1 = sext <vscale x 16 x i8> %a to <vscale x 16 x i16>
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%2 = sext <vscale x 16 x i8> %b to <vscale x 16 x i16>
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%mul = mul <vscale x 16 x i16> %1, %2
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%shr = lshr <vscale x 16 x i16> %mul, %splat
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%tr = trunc <vscale x 16 x i16> %shr to <vscale x 16 x i8>
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ret <vscale x 16 x i8> %tr
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}
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define <vscale x 8 x i16> @smulh_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
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; CHECK-LABEL: smulh_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smulh z0.h, z0.h, z1.h
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; CHECK-NEXT: ret
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%insert = insertelement <vscale x 8 x i32> undef, i32 16, i64 0
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%splat = shufflevector <vscale x 8 x i32> %insert, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
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%1 = sext <vscale x 8 x i16> %a to <vscale x 8 x i32>
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%2 = sext <vscale x 8 x i16> %b to <vscale x 8 x i32>
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%mul = mul <vscale x 8 x i32> %1, %2
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%shr = lshr <vscale x 8 x i32> %mul, %splat
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%tr = trunc <vscale x 8 x i32> %shr to <vscale x 8 x i16>
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ret <vscale x 8 x i16> %tr
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}
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define <vscale x 4 x i32> @smulh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
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; CHECK-LABEL: smulh_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smulh z0.s, z0.s, z1.s
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; CHECK-NEXT: ret
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%insert = insertelement <vscale x 4 x i64> undef, i64 32, i64 0
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%splat = shufflevector <vscale x 4 x i64> %insert, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
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%1 = sext <vscale x 4 x i32> %a to <vscale x 4 x i64>
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%2 = sext <vscale x 4 x i32> %b to <vscale x 4 x i64>
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%mul = mul <vscale x 4 x i64> %1, %2
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%shr = lshr <vscale x 4 x i64> %mul, %splat
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%tr = trunc <vscale x 4 x i64> %shr to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %tr
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}
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define <vscale x 2 x i64> @smulh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
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; CHECK-LABEL: smulh_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smulh z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%insert = insertelement <vscale x 2 x i128> undef, i128 64, i64 0
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%splat = shufflevector <vscale x 2 x i128> %insert, <vscale x 2 x i128> undef, <vscale x 2 x i32> zeroinitializer
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%1 = sext <vscale x 2 x i64> %a to <vscale x 2 x i128>
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%2 = sext <vscale x 2 x i64> %b to <vscale x 2 x i128>
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%mul = mul <vscale x 2 x i128> %1, %2
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%shr = lshr <vscale x 2 x i128> %mul, %splat
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%tr = trunc <vscale x 2 x i128> %shr to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %tr
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}
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;
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; UMULH
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;
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define <vscale x 16 x i8> @umulh_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: umulh_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umulh z0.b, z0.b, z1.b
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; CHECK-NEXT: ret
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%insert = insertelement <vscale x 16 x i16> undef, i16 8, i64 0
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%splat = shufflevector <vscale x 16 x i16> %insert, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
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%1 = zext <vscale x 16 x i8> %a to <vscale x 16 x i16>
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%2 = zext <vscale x 16 x i8> %b to <vscale x 16 x i16>
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%mul = mul <vscale x 16 x i16> %1, %2
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%shr = lshr <vscale x 16 x i16> %mul, %splat
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%tr = trunc <vscale x 16 x i16> %shr to <vscale x 16 x i8>
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ret <vscale x 16 x i8> %tr
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}
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define <vscale x 8 x i16> @umulh_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
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; CHECK-LABEL: umulh_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umulh z0.h, z0.h, z1.h
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; CHECK-NEXT: ret
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%insert = insertelement <vscale x 8 x i32> undef, i32 16, i64 0
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%splat = shufflevector <vscale x 8 x i32> %insert, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
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%1 = zext <vscale x 8 x i16> %a to <vscale x 8 x i32>
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%2 = zext <vscale x 8 x i16> %b to <vscale x 8 x i32>
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%mul = mul <vscale x 8 x i32> %1, %2
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%shr = lshr <vscale x 8 x i32> %mul, %splat
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%tr = trunc <vscale x 8 x i32> %shr to <vscale x 8 x i16>
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ret <vscale x 8 x i16> %tr
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}
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define <vscale x 4 x i32> @umulh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
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; CHECK-LABEL: umulh_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umulh z0.s, z0.s, z1.s
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; CHECK-NEXT: ret
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%insert = insertelement <vscale x 4 x i64> undef, i64 32, i64 0
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%splat = shufflevector <vscale x 4 x i64> %insert, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
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%1 = zext <vscale x 4 x i32> %a to <vscale x 4 x i64>
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%2 = zext <vscale x 4 x i32> %b to <vscale x 4 x i64>
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%mul = mul <vscale x 4 x i64> %1, %2
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%shr = lshr <vscale x 4 x i64> %mul, %splat
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%tr = trunc <vscale x 4 x i64> %shr to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %tr
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}
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define <vscale x 2 x i64> @umulh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
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; CHECK-LABEL: umulh_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umulh z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%insert = insertelement <vscale x 2 x i128> undef, i128 64, i64 0
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%splat = shufflevector <vscale x 2 x i128> %insert, <vscale x 2 x i128> undef, <vscale x 2 x i32> zeroinitializer
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%1 = zext <vscale x 2 x i64> %a to <vscale x 2 x i128>
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%2 = zext <vscale x 2 x i64> %b to <vscale x 2 x i128>
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%mul = mul <vscale x 2 x i128> %1, %2
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%shr = lshr <vscale x 2 x i128> %mul, %splat
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%tr = trunc <vscale x 2 x i128> %shr to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %tr
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}
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attributes #0 = { "target-features"="+sve2" }
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