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https://github.com/RPCS3/llvm-mirror.git
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dd84fcbdc5
This patch addresses issues arising from the fact that the index type used for subvector insertion/extraction is inconsistent between the intrinsics and SDNodes. The intrinsic forms require i64 whereas the SDNodes use the type returned by SelectionDAG::getVectorIdxTy. Rather than update the intrinsic definitions to use an overloaded index type, this patch fixes the issue by transforming the index to the correct type as required. Any loss of index bits going from i64 to a smaller type is unexpected, and will be caught by an assertion in SelectionDAG::getVectorIdxConstant. The patch also updates the documentation for INSERT_SUBVECTOR and adds an assertion to its creation to bring it in line with EXTRACT_SUBVECTOR. This necessitated changes to AArch64 which was using i64 for EXTRACT_SUBVECTOR but i32 for INSERT_SUBVECTOR. Only one test changed its codegen after updating the backend accordingly. Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D97459
195 lines
5.9 KiB
LLVM
195 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
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declare i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %a)
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declare i16 @llvm.vector.reduce.and.v1i16(<1 x i16> %a)
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declare i24 @llvm.vector.reduce.and.v1i24(<1 x i24> %a)
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declare i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %a)
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declare i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %a)
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declare i128 @llvm.vector.reduce.and.v1i128(<1 x i128> %a)
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declare i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %a)
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declare i8 @llvm.vector.reduce.and.v9i8(<9 x i8> %a)
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declare i32 @llvm.vector.reduce.and.v3i32(<3 x i32> %a)
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declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)
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declare i24 @llvm.vector.reduce.and.v4i24(<4 x i24> %a)
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declare i128 @llvm.vector.reduce.and.v2i128(<2 x i128> %a)
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declare i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %a)
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define i1 @test_v1i1(<1 x i1> %a) nounwind {
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; CHECK-LABEL: test_v1i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w0, w0, #0x1
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; CHECK-NEXT: ret
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%b = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
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ret i1 %b
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}
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define i8 @test_v1i8(<1 x i8> %a) nounwind {
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; CHECK-LABEL: test_v1i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: umov w0, v0.b[0]
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; CHECK-NEXT: ret
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%b = call i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %a)
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ret i8 %b
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}
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define i16 @test_v1i16(<1 x i16> %a) nounwind {
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; CHECK-LABEL: test_v1i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: umov w0, v0.h[0]
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; CHECK-NEXT: ret
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%b = call i16 @llvm.vector.reduce.and.v1i16(<1 x i16> %a)
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ret i16 %b
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}
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define i24 @test_v1i24(<1 x i24> %a) nounwind {
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; CHECK-LABEL: test_v1i24:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call i24 @llvm.vector.reduce.and.v1i24(<1 x i24> %a)
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ret i24 %b
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}
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define i32 @test_v1i32(<1 x i32> %a) nounwind {
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; CHECK-LABEL: test_v1i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%b = call i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %a)
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ret i32 %b
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}
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define i64 @test_v1i64(<1 x i64> %a) nounwind {
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; CHECK-LABEL: test_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%b = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %a)
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ret i64 %b
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}
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define i128 @test_v1i128(<1 x i128> %a) nounwind {
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; CHECK-LABEL: test_v1i128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call i128 @llvm.vector.reduce.and.v1i128(<1 x i128> %a)
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ret i128 %b
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}
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define i8 @test_v3i8(<3 x i8> %a) nounwind {
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; CHECK-LABEL: test_v3i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, w1
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; CHECK-NEXT: and w8, w8, w2
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; CHECK-NEXT: and w0, w8, #0xff
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; CHECK-NEXT: ret
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%b = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %a)
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ret i8 %b
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}
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define i8 @test_v9i8(<9 x i8> %a) nounwind {
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; CHECK-LABEL: test_v9i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-1
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; CHECK-NEXT: mov v1.16b, v0.16b
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; CHECK-NEXT: mov v1.b[9], w8
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; CHECK-NEXT: mov v1.b[10], w8
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; CHECK-NEXT: mov v1.b[11], w8
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; CHECK-NEXT: mov v1.b[13], w8
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; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
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; CHECK-NEXT: and v1.8b, v0.8b, v1.8b
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; CHECK-NEXT: umov w8, v1.b[1]
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; CHECK-NEXT: umov w9, v1.b[0]
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; CHECK-NEXT: and w8, w9, w8
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; CHECK-NEXT: umov w9, v1.b[2]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: umov w9, v1.b[3]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[4]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: umov w9, v1.b[5]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[6]
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: umov w9, v0.b[7]
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; CHECK-NEXT: and w0, w8, w9
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; CHECK-NEXT: ret
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%b = call i8 @llvm.vector.reduce.and.v9i8(<9 x i8> %a)
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ret i8 %b
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}
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define i32 @test_v3i32(<3 x i32> %a) nounwind {
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; CHECK-LABEL: test_v3i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: and v1.8b, v0.8b, v1.8b
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; CHECK-NEXT: mov w8, v0.s[1]
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; CHECK-NEXT: fmov w9, s1
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; CHECK-NEXT: and w0, w9, w8
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; CHECK-NEXT: ret
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%b = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> %a)
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ret i32 %b
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}
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define i1 @test_v4i1(<4 x i1> %a) nounwind {
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; CHECK-LABEL: test_v4i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: umov w10, v0.h[1]
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; CHECK-NEXT: umov w11, v0.h[0]
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; CHECK-NEXT: umov w9, v0.h[2]
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; CHECK-NEXT: and w10, w11, w10
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; CHECK-NEXT: umov w8, v0.h[3]
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; CHECK-NEXT: and w9, w10, w9
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; CHECK-NEXT: and w8, w9, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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%b = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)
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ret i1 %b
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}
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define i24 @test_v4i24(<4 x i24> %a) nounwind {
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; CHECK-LABEL: test_v4i24:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: mov w8, v0.s[1]
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: and w0, w9, w8
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; CHECK-NEXT: ret
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%b = call i24 @llvm.vector.reduce.and.v4i24(<4 x i24> %a)
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ret i24 %b
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}
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define i128 @test_v2i128(<2 x i128> %a) nounwind {
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; CHECK-LABEL: test_v2i128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and x0, x0, x2
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; CHECK-NEXT: and x1, x1, x3
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; CHECK-NEXT: ret
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%b = call i128 @llvm.vector.reduce.and.v2i128(<2 x i128> %a)
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ret i128 %b
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}
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define i32 @test_v16i32(<16 x i32> %a) nounwind {
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; CHECK-LABEL: test_v16i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: mov w8, v0.s[1]
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: and w0, w9, w8
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; CHECK-NEXT: ret
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%b = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %a)
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ret i32 %b
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}
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