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196e7f3138
Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469
39 lines
1.0 KiB
YAML
39 lines
1.0 KiB
YAML
# RUN: llc -mtriple=amdgcn-- -run-pass=liveintervals,dead-mi-elimination,simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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# This is used to fail verififcation if MachineDCE tracks LIS.
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# GCN-LABEL: name: foo
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# GCN: S_ENDPGM
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---
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name: foo
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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%10:sgpr_128 = S_LOAD_DWORDX4_IMM killed $noreg, 9, 0
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S_NOP 0, implicit-def %4:sgpr_128, implicit %10.sub1:sgpr_128
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S_CBRANCH_SCC0 %bb.3, implicit undef $scc
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S_BRANCH %bb.1
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bb.1:
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S_CBRANCH_SCC0 %bb.2, implicit undef $scc
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S_BRANCH %bb.3
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bb.2:
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%8:sreg_32_xm0 = COPY %4.sub1:sgpr_128
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%7:sreg_32_xm0 = COPY %10.sub1:sgpr_128
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S_BRANCH %bb.4
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bb.3:
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%10:sgpr_128 = S_LOAD_DWORDX4_IMM killed $noreg, 10, 0
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%7:sreg_32_xm0 = COPY %10.sub1:sgpr_128
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%8:sreg_32_xm0 = COPY %10.sub2:sgpr_128
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bb.4:
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S_NOP 0, implicit %10
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$sgpr0 = COPY %8:sreg_32_xm0
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$sgpr1 = COPY %7:sreg_32_xm0
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S_ENDPGM 0, implicit $sgpr0, implicit $sgpr1
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...
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