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https://github.com/RPCS3/llvm-mirror.git
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17322b4070
Only handle simple inter-block redefs of m0 to the same value. This avoids interference from redefs of m0 in SILoadStoreOptimzer. I was initially teaching that pass to ignore redefs of m0, but having them not exist beforehand is much simpler. This is in preparation for deleting the current special m0 handling in SIFixSGPRCopies to allow the register coalescer to handle the difficult cases. llvm-svn: 375449
367 lines
13 KiB
YAML
367 lines
13 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass=si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
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--- |
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define amdgpu_kernel void @redef_m0_same_copy() { ret void }
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define amdgpu_kernel void @multi_redef_m0_same_copy() { ret void }
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define amdgpu_kernel void @redef_m0_different_copy() { ret void }
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define amdgpu_kernel void @redef_m0_mixed_copy0() { ret void }
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define amdgpu_kernel void @redef_m0_mixed_copy1() { ret void }
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define amdgpu_kernel void @redef_m0_same_mov_imm() { ret void }
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define amdgpu_kernel void @redef_m0_different_inst0() { ret void }
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define amdgpu_kernel void @redef_m0_different_inst1() { ret void }
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define amdgpu_kernel void @redef_m0_mixed_read_m0() { ret void }
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define amdgpu_kernel void @redef_m0_same_copy_call() { ret void }
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define amdgpu_kernel void @redef_m0_same_copy_multi_block() { ret void }
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define amdgpu_kernel void @redef_m0_copy_self() { ret void }
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define amdgpu_kernel void @redef_m0_copy_physreg() { ret void }
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declare void @func()
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...
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---
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name: redef_m0_same_copy
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GCN-LABEL: name: redef_m0_same_copy
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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$m0 = COPY %1
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%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = COPY %1
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%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: multi_redef_m0_same_copy
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GCN-LABEL: name: multi_redef_m0_same_copy
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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$m0 = COPY %1
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%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = COPY %1
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$m0 = COPY %1
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%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_different_copy
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0, $sgpr1
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; GCN-LABEL: name: redef_m0_different_copy
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr1
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: $m0 = COPY [[COPY2]]
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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%2:sgpr_32 = COPY $sgpr1
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$m0 = COPY %1
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%3:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = COPY %2
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%4:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_mixed_copy0
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0, $sgpr1
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; GCN-LABEL: name: redef_m0_mixed_copy0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr1
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: $m0 = COPY [[COPY2]]
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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%2:sgpr_32 = COPY $sgpr1
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$m0 = COPY %1
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%3:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = COPY %1
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$m0 = COPY %2
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%4:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_mixed_copy1
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0, $sgpr1
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; GCN-LABEL: name: redef_m0_mixed_copy1
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr1
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: $m0 = COPY [[COPY2]]
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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%2:sgpr_32 = COPY $sgpr1
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$m0 = COPY %1
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%3:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = COPY %2
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$m0 = COPY %1
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%4:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_same_mov_imm
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GCN-LABEL: name: redef_m0_same_mov_imm
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = S_MOV_B32 -1
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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$m0 = S_MOV_B32 -1
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%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = S_MOV_B32 -1
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%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_different_inst0
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GCN-LABEL: name: redef_m0_different_inst0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: $m0 = IMPLICIT_DEF
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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$m0 = COPY %1
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%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = IMPLICIT_DEF
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%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_different_inst1
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GCN-LABEL: name: redef_m0_different_inst1
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: S_NOP 0, implicit-def $m0
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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$m0 = COPY %1
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%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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S_NOP 0, implicit-def $m0
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%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_mixed_read_m0
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0, $sgpr1
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; GCN-LABEL: name: redef_m0_mixed_read_m0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr1
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: $m0 = COPY [[COPY2]]
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: [[DS_READ_B32_2:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 128, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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%2:sgpr_32 = COPY $sgpr1
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$m0 = COPY %1
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%3:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = COPY %2
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%4:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = COPY %2
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%5:vgpr_32 = DS_READ_B32 %0, 128, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_same_copy_call
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GCN-LABEL: name: redef_m0_same_copy_call
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: dead $sgpr30_sgpr31 = SI_CALL undef $sgpr6_sgpr7, @func, csr_amdgpu_highregs
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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$m0 = COPY %1
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%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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dead $sgpr30_sgpr31 = SI_CALL undef $sgpr6_sgpr7, @func, csr_amdgpu_highregs
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$m0 = COPY %1
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%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_same_copy_multi_block
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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; GCN-LABEL: name: redef_m0_same_copy_multi_block
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: bb.1:
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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bb.0:
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liveins: $vgpr0, $sgpr0
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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$m0 = COPY %1
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%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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bb.1:
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$m0 = COPY %1
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%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_copy_self
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GCN-LABEL: name: redef_m0_copy_self
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: $m0 = COPY $m0
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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$m0 = COPY %1
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%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = COPY $m0
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%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_copy_physreg
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GCN-LABEL: name: redef_m0_copy_physreg
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = COPY $sgpr0
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: $sgpr0 = S_MOV_B32 0
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; GCN: $m0 = COPY $sgpr0
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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$m0 = COPY $sgpr0
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%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$sgpr0 = S_MOV_B32 0
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$m0 = COPY $sgpr0
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%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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