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196e7f3138
Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469
58 lines
1.6 KiB
YAML
58 lines
1.6 KiB
YAML
# RUN: llc -march=amdgcn -misched=converge -run-pass machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# Check there is no SReg_32 pressure created by DS_* instructions because of M0 use
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# CHECK: ScheduleDAGMILive::schedule starting
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# CHECK: SU({{.*}} = DS_READ_B32 {{.*}} implicit $m0, implicit $exec
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# CHECK: Pressure Diff : {{$}}
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# CHECK: SU({{.*}} DS_WRITE_B32
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---
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name: mo_pset
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_128 }
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- { id: 1, class: sgpr_64 }
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- { id: 2, class: sreg_32_xm0 }
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- { id: 3, class: sgpr_32 }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_32_xm0_xexec }
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- { id: 6, class: vgpr_32 }
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- { id: 7, class: vgpr_32 }
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- { id: 8, class: vgpr_32 }
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liveins:
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- { reg: '$sgpr4_sgpr5', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0:
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liveins: $sgpr4_sgpr5
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%1 = COPY $sgpr4_sgpr5
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%5 = S_LOAD_DWORD_IMM %1, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
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$m0 = S_MOV_B32 -1
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%7 = COPY %5
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%6 = DS_READ_B32 %7, 0, 0, implicit $m0, implicit $exec
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DS_WRITE_B32 %7, %6, 4, 0, implicit killed $m0, implicit $exec
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S_ENDPGM 0
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...
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