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9a76c13b82
This adds support for callee-pop conventions to the ARM backend so that it can ensure a call marked "tail" is actually a tail call.
46 lines
1.2 KiB
YAML
46 lines
1.2 KiB
YAML
# RUN: llc -mtriple=thumbv8 -run-pass=peephole-opt %s -o - | FileCheck %s
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# Test case for PR 47980:
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# Ensure that peephole optimization to fold move immediate doesn't unconstrain
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# the register class of the consumer.
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#
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# Check that register class for %5 is unchanged as 'tcgpr'
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# CHECK: { id: 5, class: tcgpr, preferred-register: '' }
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# CHECK: TCRETURNri killed %5
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--- |
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define i32 @foo(i32 %in) {
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ret i32 undef
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}
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...
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---
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name: foo
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registers:
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- { id: 0, class: gpr}
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- { id: 1, class: gpr }
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- { id: 2, class: rgpr }
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- { id: 3, class: gpr }
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- { id: 4, class: rgpr }
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- { id: 5, class: tcgpr }
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$r1', virtual-reg: '%1' }
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- { reg: '$r2', virtual-reg: '%2' }
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- { reg: '$r3', virtual-reg: '%3' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $r0, $r1, $r2, $r3
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%0 = COPY $r0
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%1 = COPY $r1
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%2 = COPY $r2
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%3 = COPY $r3
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%4 = t2MOVi32imm 270337
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%5 = t2ADDrr killed %2, killed %4, 14, $noreg, $noreg
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$r0 = COPY %0
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$r1 = COPY %1
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$r2 = COPY %2
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$r3 = COPY %3
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TCRETURNri killed %5, 0, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3
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...
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