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23ccb5de58
Summary: - pr42062 When compiling for MinSize, ARMTargetLowering::LowerCall decides to indirect multiple calls to a same function. However, it disconsiders the limitation that thumb1 indirect calls require the callee to be in a register from r0 to r3 (llvm limiation). If all those registers are used by arguments, the compiler dies with "error: run out of registers during register allocation". This patch tells the function IsEligibleForTailCallOptimization if we intend to perform indirect calls, as to avoid tail call optimization. Reviewers: dmgreen, efriedma Reviewed By: efriedma Subscribers: javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62683 llvm-svn: 362366
39 lines
1.3 KiB
LLVM
39 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -o - %s 2>&1 | FileCheck %s --implicit-check-not=error
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target triple = "thumbv8m.base-arm-none-eabi"
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@foo = external global i8
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declare i32 @bar(i8* nocapture, i32, i32, i8* nocapture)
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define void @food(i8* %a) #0 {
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; CHECK-LABEL: food:
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; CHECK: mov [[ARG0:r[4-7]]], r0
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; CHECK-NEXT: movs r1, #8
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; CHECK-NEXT: movs r2, #1
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; CHECK-NEXT: ldr [[FOO_R:r[4-7]]], [[FOO_ADDR:\..*]]
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; CHECK-NEXT: ldr [[BAR_R:r[4-7]]], [[BAR_ADDR:\..*]]
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; CHECK-NEXT: mov r3, [[FOO_R]]
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; CHECK-NEXT: blx [[BAR_R]]
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; CHECK-NEXT: movs r1, #9
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; CHECK-NEXT: movs r2, #0
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; CHECK-NEXT: mov r0, [[ARG0]]
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; CHECK-NEXT: mov r3, [[FOO_R]]
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; CHECK-NEXT: blx [[BAR_R]]
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; CHECK-NEXT: movs r1, #7
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; CHECK-NEXT: movs r2, #2
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; CHECK-NEXT: mov r0, [[ARG0]]
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; CHECK-NEXT: mov r3, [[FOO_R]]
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; CHECK-NEXT: blx [[BAR_R]]
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; CHECK-NEXT: pop {r4, r5, r6, pc}
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; CHECK: [[FOO_ADDR]]:
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; CHECK-NEXT: .long foo
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; CHECK: [[BAR_ADDR]]:
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; CHECK-NEXT: .long bar
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entry:
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%0 = tail call i32 @bar(i8* %a, i32 8, i32 1, i8* nonnull @foo)
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%1 = tail call i32 @bar(i8* %a, i32 9, i32 0, i8* nonnull @foo)
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%2 = tail call i32 @bar(i8* %a, i32 7, i32 2, i8* nonnull @foo)
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ret void
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}
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attributes #0 = { minsize "target-cpu"="cortex-m23" }
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