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llvm-mirror/test/CodeGen/X86/lwp-intrinsics.ll
Wang, Pengfei c275334e12 [CodeGen][X86] Remove unused trivial check-prefixes from all CodeGen/X86 directory. 
I had manually removed unused prefixes from CodeGen/X86 directory for more than 100 tests.
I checked the change history for each of them at the beginning, and then I mainly focused on the format since I found all of the unused prefixes were result from either insensible copy or residuum after functional update.
I think it's OK to remove the remaining X86 tests by script now. I wrote a rough script which works for me in most tests. I put it in llvm/utils temporarily for review and hope it may help other components owners.
The tests in this patch are all generated by the tool and checked by update tool for the autogenerated tests. I skimmed them and checked about 30 tests and didn't find any unexpected changes.

Reviewed By: mtrofin, MaskRay

Differential Revision: https://reviews.llvm.org/D91496
2020-11-16 09:45:55 +08:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+lwp | FileCheck %s --check-prefixes=X86,X86_LWP
; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver1 | FileCheck %s --check-prefixes=X86,X86_BDVER1
; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver2 | FileCheck %s --check-prefixes=X86,X86_BDVER2
; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver3 | FileCheck %s --check-prefixes=X86,X86_BDVER3
; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver4 | FileCheck %s --check-prefixes=X86,X86_BDVER4
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+lwp | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver1 | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver2 | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver3 | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver4 | FileCheck %s --check-prefix=X64
define void @test_llwpcb(i8 *%a0) nounwind {
; X86-LABEL: test_llwpcb:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: llwpcb %eax
; X86-NEXT: retl
;
; X64-LABEL: test_llwpcb:
; X64: # %bb.0:
; X64-NEXT: llwpcb %rdi
; X64-NEXT: retq
tail call void @llvm.x86.llwpcb(i8 *%a0)
ret void
}
define i8* @test_slwpcb(i8 *%a0) nounwind {
; X86-LABEL: test_slwpcb:
; X86: # %bb.0:
; X86-NEXT: slwpcb %eax
; X86-NEXT: retl
;
; X64-LABEL: test_slwpcb:
; X64: # %bb.0:
; X64-NEXT: slwpcb %rax
; X64-NEXT: retq
%1 = tail call i8* @llvm.x86.slwpcb()
ret i8 *%1
}
define i8 @test_lwpins32_rri(i32 %a0, i32 %a1) nounwind {
; X86_LWP-LABEL: test_lwpins32_rri:
; X86_LWP: # %bb.0:
; X86_LWP-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86_LWP-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86_LWP-NEXT: addl %ecx, %ecx
; X86_LWP-NEXT: lwpins $-1985229329, %ecx, %eax # imm = 0x89ABCDEF
; X86_LWP-NEXT: setb %al
; X86_LWP-NEXT: retl
;
; X86_BDVER1-LABEL: test_lwpins32_rri:
; X86_BDVER1: # %bb.0:
; X86_BDVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86_BDVER1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86_BDVER1-NEXT: addl %ecx, %ecx
; X86_BDVER1-NEXT: lwpins $-1985229329, %ecx, %eax # imm = 0x89ABCDEF
; X86_BDVER1-NEXT: setb %al
; X86_BDVER1-NEXT: retl
;
; X86_BDVER2-LABEL: test_lwpins32_rri:
; X86_BDVER2: # %bb.0:
; X86_BDVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86_BDVER2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86_BDVER2-NEXT: addl %ecx, %ecx
; X86_BDVER2-NEXT: lwpins $-1985229329, %ecx, %eax # imm = 0x89ABCDEF
; X86_BDVER2-NEXT: setb %al
; X86_BDVER2-NEXT: retl
;
; X86_BDVER3-LABEL: test_lwpins32_rri:
; X86_BDVER3: # %bb.0:
; X86_BDVER3-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86_BDVER3-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86_BDVER3-NEXT: addl %ecx, %ecx
; X86_BDVER3-NEXT: lwpins $-1985229329, %ecx, %eax # imm = 0x89ABCDEF
; X86_BDVER3-NEXT: setb %al
; X86_BDVER3-NEXT: retl
;
; X86_BDVER4-LABEL: test_lwpins32_rri:
; X86_BDVER4: # %bb.0:
; X86_BDVER4-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86_BDVER4-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86_BDVER4-NEXT: addl %ecx, %ecx
; X86_BDVER4-NEXT: lwpins $-1985229329, %ecx, %eax # imm = 0x89ABCDEF
; X86_BDVER4-NEXT: setb %al
; X86_BDVER4-NEXT: retl
;
; X64-LABEL: test_lwpins32_rri:
; X64: # %bb.0:
; X64-NEXT: addl %esi, %esi
; X64-NEXT: lwpins $-1985229329, %esi, %edi # imm = 0x89ABCDEF
; X64-NEXT: setb %al
; X64-NEXT: retq
%1 = add i32 %a1, %a1
%2 = tail call i8 @llvm.x86.lwpins32(i32 %a0, i32 %1, i32 2309737967)
ret i8 %2
}
define i8 @test_lwpins32_rmi(i32 %a0, i32 *%p1) nounwind {
; X86-LABEL: test_lwpins32_rmi:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: lwpins $1985229328, (%eax), %ecx # imm = 0x76543210
; X86-NEXT: setb %al
; X86-NEXT: retl
;
; X64-LABEL: test_lwpins32_rmi:
; X64: # %bb.0:
; X64-NEXT: lwpins $1985229328, (%rsi), %edi # imm = 0x76543210
; X64-NEXT: setb %al
; X64-NEXT: retq
%a1 = load i32, i32 *%p1
%1 = tail call i8 @llvm.x86.lwpins32(i32 %a0, i32 %a1, i32 1985229328)
ret i8 %1
}
define void @test_lwpval32_rri(i32 %a0, i32 %a1) nounwind {
; X86_LWP-LABEL: test_lwpval32_rri:
; X86_LWP: # %bb.0:
; X86_LWP-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86_LWP-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86_LWP-NEXT: addl %ecx, %ecx
; X86_LWP-NEXT: lwpval $-19088744, %ecx, %eax # imm = 0xFEDCBA98
; X86_LWP-NEXT: retl
;
; X86_BDVER1-LABEL: test_lwpval32_rri:
; X86_BDVER1: # %bb.0:
; X86_BDVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86_BDVER1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86_BDVER1-NEXT: addl %ecx, %ecx
; X86_BDVER1-NEXT: lwpval $-19088744, %ecx, %eax # imm = 0xFEDCBA98
; X86_BDVER1-NEXT: retl
;
; X86_BDVER2-LABEL: test_lwpval32_rri:
; X86_BDVER2: # %bb.0:
; X86_BDVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86_BDVER2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86_BDVER2-NEXT: addl %ecx, %ecx
; X86_BDVER2-NEXT: lwpval $-19088744, %ecx, %eax # imm = 0xFEDCBA98
; X86_BDVER2-NEXT: retl
;
; X86_BDVER3-LABEL: test_lwpval32_rri:
; X86_BDVER3: # %bb.0:
; X86_BDVER3-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86_BDVER3-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86_BDVER3-NEXT: addl %ecx, %ecx
; X86_BDVER3-NEXT: lwpval $-19088744, %ecx, %eax # imm = 0xFEDCBA98
; X86_BDVER3-NEXT: retl
;
; X86_BDVER4-LABEL: test_lwpval32_rri:
; X86_BDVER4: # %bb.0:
; X86_BDVER4-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86_BDVER4-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86_BDVER4-NEXT: addl %ecx, %ecx
; X86_BDVER4-NEXT: lwpval $-19088744, %ecx, %eax # imm = 0xFEDCBA98
; X86_BDVER4-NEXT: retl
;
; X64-LABEL: test_lwpval32_rri:
; X64: # %bb.0:
; X64-NEXT: addl %esi, %esi
; X64-NEXT: lwpval $-19088744, %esi, %edi # imm = 0xFEDCBA98
; X64-NEXT: retq
%1 = add i32 %a1, %a1
tail call void @llvm.x86.lwpval32(i32 %a0, i32 %1, i32 4275878552)
ret void
}
define void @test_lwpval32_rmi(i32 %a0, i32 *%p1) nounwind {
; X86-LABEL: test_lwpval32_rmi:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: lwpval $305419896, (%eax), %ecx # imm = 0x12345678
; X86-NEXT: retl
;
; X64-LABEL: test_lwpval32_rmi:
; X64: # %bb.0:
; X64-NEXT: lwpval $305419896, (%rsi), %edi # imm = 0x12345678
; X64-NEXT: retq
%a1 = load i32, i32 *%p1
tail call void @llvm.x86.lwpval32(i32 %a0, i32 %a1, i32 305419896)
ret void
}
declare void @llvm.x86.llwpcb(i8*) nounwind
declare i8* @llvm.x86.slwpcb() nounwind
declare i8 @llvm.x86.lwpins32(i32, i32, i32) nounwind
declare void @llvm.x86.lwpval32(i32, i32, i32) nounwind
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