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29f0c6f517
We need to cover each register class with a register bank. llvm-svn: 265629
58 lines
2.1 KiB
C++
58 lines
2.1 KiB
C++
//===- AArch64RegisterBankInfo -----------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the RegisterBankInfo class for AArch64.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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namespace llvm {
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class TargetRegisterInfo;
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namespace AArch64 {
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enum {
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GPRRegBankID = 0, /// General Purpose Registers: W, X.
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FPRRegBankID = 1, /// Floating Point/Vector Registers: B, H, S, D, Q.
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CCRRegBankID = 2, /// Conditional register: NZCV.
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NumRegisterBanks
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};
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} // End AArch64 namespace.
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/// This class provides the information for the target register banks.
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class AArch64RegisterBankInfo : public RegisterBankInfo {
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public:
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AArch64RegisterBankInfo(const TargetRegisterInfo &TRI);
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/// Get the cost of a copy from \p B to \p A, or put differently,
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/// get the cost of A = COPY B.
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unsigned copyCost(const RegisterBank &A,
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const RegisterBank &B) const override;
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/// Get a register bank that covers \p RC.
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///
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/// \pre \p RC is a user-defined register class (as opposed as one
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/// generated by TableGen).
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///
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/// \note The mapping RC -> RegBank could be built while adding the
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/// coverage for the register banks. However, we do not do it, because,
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/// at least for now, we only need this information for register classes
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/// that are used in the description of instruction. In other words,
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/// there are just a handful of them and we do not want to waste space.
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///
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/// \todo This should be TableGen'ed.
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const RegisterBank &
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getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
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};
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} // End llvm namespace.
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#endif
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