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544972b656
When SelectionDAG merges consecutive stores and loads in MergeConsecutiveStores, it does not set dereferenceable flag for a created load instruction. This results in an assertion failure if SelectionDAG commonizes this load instruction with other load instructions, as well as it may miss optimization opportunities. This patch sat dereferenceable flag for the newly created load instruction if all the load instructions to be merged are dereferenceable. Differential Revision: https://reviews.llvm.org/D34679 llvm-svn: 306404
25 lines
918 B
LLVM
25 lines
918 B
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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; This code causes an assertion failure if dereferenceable flag is not properly set when in merging consecutive stores
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; CHECK-LABEL: func:
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; CHECK: lxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOT: lxvd2x
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; CHECK: stxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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define <2 x i64> @func(i64* %pdst) {
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entry:
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%a = alloca [4 x i64], align 8
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%psrc0 = bitcast [4 x i64]* %a to i64*
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%psrc1 = getelementptr inbounds i64, i64* %psrc0, i64 1
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%d0 = load i64, i64* %psrc0
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%d1 = load i64, i64* %psrc1
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%pdst0 = getelementptr inbounds i64, i64* %pdst, i64 0
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%pdst1 = getelementptr inbounds i64, i64* %pdst, i64 1
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store i64 %d0, i64* %pdst0, align 8
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store i64 %d1, i64* %pdst1, align 8
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%psrcd = bitcast [4 x i64]* %a to <2 x i64>*
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%vec = load <2 x i64>, <2 x i64>* %psrcd
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ret <2 x i64> %vec
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}
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