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AArch64
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[AArch64] Generate rev16/rev32 from bswap + srl when upper bits are known zero.
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2016-05-26 19:41:33 +00:00 |
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AMDGPU
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AMDGPU: Cleanup vector insert/extract tests
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2016-05-28 00:51:06 +00:00 |
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ARM
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Fix default reloc model on ARM.
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2016-05-28 10:41:15 +00:00 |
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BPF
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[BPF] Remove exit-on-error from tests (PR27768, PR27769)
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2016-05-30 08:28:34 +00:00 |
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Generic
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llc: Rework -run-pass option
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2016-05-10 01:32:44 +00:00 |
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Hexagon
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[Hexagon] Enable the post-RA scheduler
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2016-05-26 19:44:28 +00:00 |
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Inputs
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
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Lanai
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[lanai] Change reloc to use PIC_ by default and cleanup.
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2016-05-20 21:41:53 +00:00 |
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Mips
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[mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine verifier.
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2016-05-19 10:42:14 +00:00 |
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MIR
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Add test/CodeGen/MIR/Hexagon/lit.local.cfg
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2016-05-26 18:35:45 +00:00 |
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MSP430
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NVPTX
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[NVPTX] Added NVVMIntrRange pass
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2016-05-26 17:02:56 +00:00 |
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PowerPC
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Move and add comments to the top for tailcall-string-rvo.ll
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2016-05-25 17:01:09 +00:00 |
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SPARC
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[SPARC] Fix 8 and 16-bit atomic load and store.
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2016-05-23 20:33:00 +00:00 |
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SystemZ
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[SystemZ] Fix register ordering for BinaryRRF instructions
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2016-05-18 13:24:57 +00:00 |
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Thumb
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ARM: stop emitting blx instructions for most calls on MachO.
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2016-05-10 19:17:47 +00:00 |
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Thumb2
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ARM: stop emitting blx instructions for most calls on MachO.
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2016-05-10 19:17:47 +00:00 |
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WebAssembly
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[WebAssembly] Put __stack_pointer in the offset field of loads and stores.
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2016-05-24 23:47:41 +00:00 |
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WinEH
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
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X86
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[X86] Remove SSE/AVX unaligned store intrinsics as clang no longer uses them. Auto upgrade to native unaligned store instructions.
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2016-05-30 23:15:56 +00:00 |
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XCore
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
