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38a34d7651
Generate extract instructions (via intrinsics) before the DAG combiner folds shifts into unrecognizable forms. llvm-svn: 242163
18 lines
526 B
LLVM
18 lines
526 B
LLVM
; RUN: llc -march=hexagon -hexagon-extract=0 < %s | FileCheck %s
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; Check that we generate fused logical and with shift instruction.
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; Disable "extract" generation, since it may eliminate the and/lsr.
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; CHECK: r{{[0-9]+}} = and(#15, lsr(r{{[0-9]+}}, #{{[0-9]+}})
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define i32 @main(i16* %a, i16* %b) nounwind {
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entry:
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%0 = load i16, i16* %a, align 2
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%conv1 = sext i16 %0 to i32
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%shr1 = ashr i32 %conv1, 3
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%and1 = and i32 %shr1, 15
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%conv2 = trunc i32 %and1 to i16
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store i16 %conv2, i16* %b, align 2
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ret i32 0
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}
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