mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-21 03:53:04 +02:00
0eb872067d
This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
157 lines
3.0 KiB
YAML
157 lines
3.0 KiB
YAML
# RUN: llc -run-pass x86-fixup-bw-insts -mtriple=x86_64-- -o /dev/null %s 2>&1 | FileCheck %s
|
|
|
|
# Verify that we correctly deal with the flag edge cases when replacing
|
|
# copies by bigger copies, which is a pretty unusual transform.
|
|
|
|
--- |
|
|
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
|
|
|
|
define i8 @test_movb_killed(i8 %a0) {
|
|
ret i8 %a0
|
|
}
|
|
|
|
define i8 @test_movb_impuse(i8 %a0) {
|
|
ret i8 %a0
|
|
}
|
|
|
|
define i8 @test_movb_impdef_gr64(i8 %a0) {
|
|
ret i8 %a0
|
|
}
|
|
|
|
define i8 @test_movb_impdef_gr32(i8 %a0) {
|
|
ret i8 %a0
|
|
}
|
|
|
|
define i8 @test_movb_impdef_gr16(i8 %a0) {
|
|
ret i8 %a0
|
|
}
|
|
|
|
define i16 @test_movw_impdef_gr32(i16 %a0) {
|
|
ret i16 %a0
|
|
}
|
|
|
|
define i16 @test_movw_impdef_gr64(i16 %a0) {
|
|
ret i16 %a0
|
|
}
|
|
|
|
...
|
|
|
|
---
|
|
name: test_movb_killed
|
|
allVRegsAllocated: true
|
|
isSSA: false
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '%edi' }
|
|
body: |
|
|
bb.0 (%ir-block.0):
|
|
liveins: %edi
|
|
|
|
; CHECK: %eax = MOV32rr undef %edi, implicit %dil
|
|
%al = MOV8rr killed %dil
|
|
RETQ killed %al
|
|
|
|
...
|
|
|
|
---
|
|
name: test_movb_impuse
|
|
allVRegsAllocated: true
|
|
isSSA: false
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '%edi' }
|
|
body: |
|
|
bb.0 (%ir-block.0):
|
|
liveins: %edi
|
|
|
|
; CHECK: %eax = MOV32rr undef %edi, implicit %dil
|
|
%al = MOV8rr %dil, implicit %edi
|
|
RETQ killed %al
|
|
|
|
...
|
|
|
|
---
|
|
name: test_movb_impdef_gr64
|
|
allVRegsAllocated: true
|
|
isSSA: false
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '%edi' }
|
|
body: |
|
|
bb.0 (%ir-block.0):
|
|
liveins: %edi
|
|
|
|
; CHECK: %eax = MOV32rr undef %edi, implicit %dil, implicit-def %rax
|
|
%al = MOV8rr %dil, implicit-def %rax
|
|
RETQ killed %al
|
|
|
|
...
|
|
|
|
---
|
|
name: test_movb_impdef_gr32
|
|
allVRegsAllocated: true
|
|
isSSA: false
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '%edi' }
|
|
body: |
|
|
bb.0 (%ir-block.0):
|
|
liveins: %edi
|
|
|
|
; CHECK: %eax = MOV32rr undef %edi, implicit %dil
|
|
%al = MOV8rr %dil, implicit-def %eax
|
|
RETQ killed %al
|
|
|
|
...
|
|
|
|
---
|
|
name: test_movb_impdef_gr16
|
|
allVRegsAllocated: true
|
|
isSSA: false
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '%edi' }
|
|
body: |
|
|
bb.0 (%ir-block.0):
|
|
liveins: %edi
|
|
|
|
; CHECK: %eax = MOV32rr undef %edi, implicit %dil
|
|
%al = MOV8rr %dil, implicit-def %ax
|
|
RETQ killed %al
|
|
|
|
...
|
|
|
|
---
|
|
name: test_movw_impdef_gr32
|
|
allVRegsAllocated: true
|
|
isSSA: false
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '%edi' }
|
|
body: |
|
|
bb.0 (%ir-block.0):
|
|
liveins: %edi
|
|
|
|
; CHECK: %eax = MOV32rr undef %edi, implicit %di
|
|
%ax = MOV16rr %di, implicit-def %eax
|
|
RETQ killed %ax
|
|
|
|
...
|
|
|
|
---
|
|
name: test_movw_impdef_gr64
|
|
allVRegsAllocated: true
|
|
isSSA: false
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '%edi' }
|
|
body: |
|
|
bb.0 (%ir-block.0):
|
|
liveins: %edi
|
|
|
|
; CHECK: %eax = MOV32rr undef %edi, implicit %di, implicit-def %rax
|
|
%ax = MOV16rr %di, implicit-def %rax
|
|
RETQ killed %ax
|
|
|
|
...
|