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llvm-mirror/test/CodeGen/MIR/X86
Craig Topper a26008def0 [X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.
Rename the old versions that use FR32/FR64 to MOVSSrm_alt/MOVSDrm_alt.

Use the new versions in patterns that previously used a COPY_TO_REGCLASS
to VR128. These patterns expect the upper bits to be zero. The
current set up appears to work, but I'm not sure we should be
enforcing upper bits being zero through a COPY_TO_REGCLASS.

I wanted to flip the arrangement and use a COPY_TO_REGCLASS to
FR32/FR64 for the patterns that need an f32/f64 result, but that
complicated fastisel and globalisel.

I've been doing some experiments with reducing some isel patterns
and ended up in a situation where I had a
(SUBREG_TO_REG (COPY_TO_RECLASS (VMOVSSrm), VR128)) and our
post-isel peephole was unable to avoid using an instruction for
the SUBREG_TO_REG due to the COPY_TO_REGCLASS. Having a VR128
instruction removes the COPY_TO_REGCLASS that was breaking this.

llvm-svn: 363643
2019-06-18 03:23:11 +00:00
..
auto-successor.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
basic-block-liveins.mir
basic-block-not-at-start-of-line-error.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
block-address-operands.mir
branch-folder-with-label.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
branch-probabilities.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
callee-saved-info.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
cfi-def-cfa-offset.mir
cfi-def-cfa-register.mir
cfi-offset.mir
constant-pool-item-redefinition-error.mir
constant-pool.mir
constant-value-error.mir
copyIRflags.mir
dead-register-flag.mir
def-register-already-tied-error.mir
diexpr-win32.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
duplicate-memory-operand-flag.mir
duplicate-register-flag-error.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
early-clobber-register-flag.mir
empty0.mir
empty1.mir
empty2.mir
escape-function-name.ll
expected-align-in-memory-operand.mir
expected-alignment-after-align-in-memory-operand.mir
expected-basic-block-at-start-of-body.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
expected-block-reference-in-blockaddress.mir
expected-comma-after-cfi-register.mir
expected-comma-after-memory-operand.mir
expected-different-implicit-operand.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
expected-different-implicit-register-flag.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
expected-function-reference-after-blockaddress.mir
expected-global-value-after-blockaddress.mir
expected-integer-after-offset-sign.mir
expected-integer-after-tied-def.mir
expected-integer-in-successor-weight.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
expected-load-or-store-in-memory-operand.mir
expected-machine-operand.mir
expected-metadata-node-after-debug-location.mir
expected-metadata-node-after-exclaim.mir
expected-metadata-node-in-stack-object.mir
expected-named-register-in-allocation-hint.mir
expected-named-register-in-callee-saved-register.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
expected-named-register-in-functions-livein.mir
expected-named-register-livein.mir
expected-newline-at-end-of-list.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
expected-number-after-bb.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
expected-offset-after-cfi-operand.mir
expected-pointer-value-in-memory-operand.mir
expected-positive-alignment-after-align.mir
expected-power-of-2-after-align.mir
expected-register-after-cfi-operand.mir
expected-register-after-flags.mir
expected-size-integer-after-memory-operation2.mir
expected-size-integer-after-memory-operation.mir
expected-stack-object.mir
expected-subregister-after-colon.mir
expected-target-flag-name.mir
expected-tied-def-after-lparen.mir
expected-value-in-memory-operand.mir
expected-virtual-register-in-functions-livein.mir
external-symbol-operands.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
fastmath.mir
fixed-stack-di.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
fixed-stack-memory-operands.mir
fixed-stack-object-redefinition-error.mir
fixed-stack-objects.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
frame-info-save-restore-points.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
frame-info-stack-references.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
frame-setup-instruction-flag.mir
function-liveins.mir
generic-instr-type.mir
global-value-operands.mir
immediate-operands.mir
implicit-register-flag.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
inline-asm-registers.mir
inline-asm.mir
instr-symbols-and-mcsymbol-operands.mir
instructions-debug-location.mir
invalid-constant-pool-item.mir
invalid-debug-location.mir
invalid-metadata-node-type.mir
invalid-target-flag-name.mir
invalid-tied-def-index-error.mir
jump-table-info.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
jump-table-redefinition-error.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
killed-register-flag.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
large-cfi-offset-number-error.mir
large-immediate-operand-error.mir
large-index-number-error.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
large-offset-number-error.mir
large-size-in-memory-operand-error.mir
lit.local.cfg
liveout-register-mask.mir
machine-basic-block-operands.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
machine-instructions.mir
machine-verifier.mir
memory-operands.mir [X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class. 2019-06-18 03:23:11 +00:00
metadata-operands.mir
missing-closing-quote.mir
missing-comma.mir
missing-implicit-operand.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
named-registers.mir
newline-handling.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
null-register-operands.mir
pr38773.mir
register-mask-operands.mir
register-operand-class-invalid0.mir
register-operand-class-invalid1.mir
register-operand-class.mir
register-operands-target-flag-error.mir
renamable-register-flag.mir
roundtrip.mir
simple-register-allocation-hints.mir
spill-slot-fixed-stack-object-aliased.mir
spill-slot-fixed-stack-object-immutable.mir
spill-slot-fixed-stack-objects.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
stack-object-debug-info.mir
stack-object-invalid-name.mir
stack-object-operand-name-mismatch-error.mir
stack-object-operands.mir
stack-object-redefinition-error.mir
stack-objects.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
standalone-register-error.mir
subreg-on-physreg.mir
subregister-index-operands.mir
subregister-operands.mir
successor-basic-blocks-weights.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
successor-basic-blocks.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
tied-def-operand-invalid.mir
tied-physical-regs-match.mir
undef-register-flag.mir
undefined-fixed-stack-object.mir
undefined-global-value.mir
undefined-ir-block-in-blockaddress.mir
undefined-ir-block-slot-in-blockaddress.mir
undefined-jump-table-id.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
undefined-named-global-value.mir
undefined-register-class.mir
undefined-stack-object.mir
undefined-value-in-memory-operand.mir
undefined-virtual-register.mir
unexpected-type-phys.mir
unknown-instruction.mir
unknown-machine-basic-block.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
unknown-metadata-keyword.mir
unknown-metadata-node.mir
unknown-named-machine-basic-block.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
unknown-register.mir
unknown-subregister-index-op.mir
unknown-subregister-index.mir
unreachable_block.ll
unrecognized-character.mir
variable-sized-stack-object-size-error.mir
variable-sized-stack-objects.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
virtual-register-redefinition-error.mir
virtual-registers.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
zero-probability.mir