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llvm-mirror/test/CodeGen
Nicolai Haehnle 364da50d63 AMDGPU: Add amdgpu-ps-wqm-outputs function attributes
Summary:
The presence of this attribute indicates that VGPR outputs should be computed
in whole quad mode. This will be used by Mesa for prolog pixel shaders, so
that derivatives can be taken of shader inputs computed by the prolog, fixing
a bug.

The generated code could certainly be improved: if a prolog pixel shader is
used (which isn't common in modern OpenGL - they're used for gl_Color, polygon
stipples, and forcing per-sample interpolation), Mesa will use this attribute
unconditionally, because it has to be conservative. So WQM may be used in the
prolog when it isn't really needed, and furthermore a silly back-and-forth
switch is likely to happen at the boundary between prolog and main shader
parts.

Fixing this is a bit involved: we'd first have to add a mechanism by which
LLVM writes the WQM-related input requirements to the main shader part binary,
and then Mesa specializes the prolog part accordingly. At that point, we may
as well just compile a monolithic shader...

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95130

Reviewers: arsenm, tstellarAMD, mareko

Subscribers: arsenm, llvm-commits, kzhuravl

Differential Revision: http://reviews.llvm.org/D20839

llvm-svn: 272063
2016-06-07 21:37:17 +00:00
..
AArch64 Reapply [AArch64] Fix isLegalAddImmediate() to return true for valid negative values. 2016-06-07 16:48:43 +00:00
AMDGPU AMDGPU: Add amdgpu-ps-wqm-outputs function attributes 2016-06-07 21:37:17 +00:00
ARM Revert "[MBP] Reduce code size by running tail merging in MBP." 2016-06-07 15:17:21 +00:00
BPF [BPF] Remove exit-on-error from tests (PR27768, PR27769) 2016-05-30 08:28:34 +00:00
Generic
Hexagon [Hexagon] Enable the post-RA scheduler 2016-05-26 19:44:28 +00:00
Inputs
Lanai [lanai] Change reloc to use PIC_ by default and cleanup. 2016-05-20 21:41:53 +00:00
Mips [mips] Implement 'la' macro in PIC mode for O32. 2016-06-03 09:53:06 +00:00
MIR MIR: Support MachineMemOperands without associated value 2016-06-04 00:06:31 +00:00
MSP430
NVPTX [NVPTX] Added NVVMIntrRange pass 2016-05-26 17:02:56 +00:00
PowerPC [PowerPC] Support multiple return values with fast isel 2016-06-07 12:48:22 +00:00
SPARC [Sparc] Allow passing of empty structs. 2016-06-01 08:48:56 +00:00
SystemZ [SystemZ] Fix register ordering for BinaryRRF instructions 2016-05-18 13:24:57 +00:00
Thumb [Thumb-1] Add optimized constant materialization for integers [256..512) 2016-06-07 13:10:14 +00:00
Thumb2
WebAssembly [WebAssembly] Emit type signatures for declared functions 2016-06-03 18:34:36 +00:00
WinEH
X86 [X86][SSE4A] Regenerated SSE4A intrinsics tests 2016-06-07 21:15:45 +00:00
XCore