1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 12:12:47 +01:00
llvm-mirror/test/CodeGen/AArch64/arm64-blockaddress.ll
Evandro Menezes 5d88cb6cf6 [AArch64] Generate literals by the little end
ARM seems to prefer that long literals be formed from their little end in
order to promote the fusion of the instrs pairs MOV/MOVK and MOVK/MOVK on
Cortex A57 and others (v.  "Cortex A57 Software Optimisation Guide", section
4.14).

Differential revision: https://reviews.llvm.org/D28697

llvm-svn: 292422
2017-01-18 18:57:08 +00:00

31 lines
1.0 KiB
LLVM

; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefix=CHECK-LINUX
; RUN: llc < %s -mtriple=arm64-linux-gnu -code-model=large| FileCheck %s --check-prefix=CHECK-LARGE
; rdar://9188695
define i64 @t() nounwind ssp {
entry:
; CHECK-LABEL: t:
; CHECK: adrp [[REG:x[0-9]+]], Ltmp1@PAGE
; CHECK: add {{x[0-9]+}}, [[REG]], Ltmp1@PAGEOFF
; CHECK-LINUX-LABEL: t:
; CHECK-LINUX: adrp [[REG:x[0-9]+]], .Ltmp1
; CHECK-LINUX: add {{x[0-9]+}}, [[REG]], :lo12:.Ltmp1
; CHECK-LARGE-LABEL: t:
; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g0_nc:[[DEST_LBL:.Ltmp[0-9]+]]
; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g1_nc:[[DEST_LBL]]
; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g3:[[DEST_LBL]]
%recover = alloca i64, align 8
store volatile i64 ptrtoint (i8* blockaddress(@t, %mylabel) to i64), i64* %recover, align 8
br label %mylabel
mylabel:
%tmp = load volatile i64, i64* %recover, align 8
ret i64 %tmp
}